Difference between revisions of "84PCE:Ports:0000 Unknowns"

From WikiTI
Jump to: navigation, search
(0000 Range)
(0000 Range)
Line 12: Line 12:
 
|[[:84PCE:Ports:0000|0000]]
 
|[[:84PCE:Ports:0000|0000]]
 
|03
 
|03
|D3
 
 
|CPU Speed Control
 
|CPU Speed Control
 
|-
 
|-
 
|[[:84PCE:Ports:0001|0001]]
 
|[[:84PCE:Ports:0001|0001]]
 
|03
 
|03
|13
 
 
|OS Timer Control
 
|OS Timer Control
 
|-
 
|-
 
|[[:84PCE:Ports:0002|0002]]
 
|[[:84PCE:Ports:0002|0002]]
 
|
 
|
|??
 
 
|Read only, value can change
 
|Read only, value can change
 
|-
 
|-
 
|[[:84PCE:Ports:0005|0005]]
 
|[[:84PCE:Ports:0005|0005]]
 
|76
 
|76
|??
 
 
|Set bit 5 to freeze, bit 6 affects backlight
 
|Set bit 5 to freeze, bit 6 affects backlight
 
|-
 
|-
 
|[[:84PCE:Ports:0006|0006]]
 
|[[:84PCE:Ports:0006|0006]]
 
|03
 
|03
|03?
 
 
|Display refresh
 
|Display refresh
 
|-
 
|-
 
|[[:84PCE:Ports:0007|0007]]
 
|[[:84PCE:Ports:0007|0007]]
 
|B7
 
|B7
|FF
 
 
|Latches values written
 
|Latches values written
 
|-
 
|-
 
|[[:84PCE:Ports:0008|0008]]
 
|[[:84PCE:Ports:0008|0008]]
|7F
 
 
|7F
 
|7F
 
|Cannot change value
 
|Cannot change value
Line 47: Line 40:
 
|[[:84PCE:Ports:0009|0009]]
 
|[[:84PCE:Ports:0009|0009]]
 
|37
 
|37
|??
 
 
|Power control system
 
|Power control system
 
|-
 
|-
 
|[[:84PCE:Ports:000A|000A]]
 
|[[:84PCE:Ports:000A|000A]]
 
|FD
 
|FD
|FF
 
 
|Latches value written
 
|Latches value written
 
|-
 
|-
 
|[[:84PCE:Ports:000C|000C]]
 
|[[:84PCE:Ports:000C|000C]]
 
|00
 
|00
|FF
 
 
|Latches value written
 
|Latches value written
 
|-
 
|-
 
|[[:84PCE:Ports:000D|000D]]
 
|[[:84PCE:Ports:000D|000D]]
|FF
 
 
|FF
 
|FF
 
|Bit 0: Freeze if reset<br />Bit 1: Crash if reset<br />Bit 2: No apparent effect if reset<br />Bit 3: Reset to disable VRAM? Upon set, VRAM is garbage.<br />Bits [7:4]Possibly last value written
 
|Bit 0: Freeze if reset<br />Bit 1: Crash if reset<br />Bit 2: No apparent effect if reset<br />Bit 3: Reset to disable VRAM? Upon set, VRAM is garbage.<br />Bits [7:4]Possibly last value written
Line 67: Line 56:
 
|[[:84PCE:Ports:000E|000E]]
 
|[[:84PCE:Ports:000E|000E]]
 
|0A
 
|0A
|FF
 
 
|Latches value written
 
|Latches value written
 
|-
 
|-
 
|[[:84PCE:Ports:000F|000F]]
 
|[[:84PCE:Ports:000F|000F]]
 
|42
 
|42
|?3
 
 
|High nibble may be a status, low 2 bits latch value written
 
|High nibble may be a status, low 2 bits latch value written
 
|-
 
|-
 
|[[:84PCE:Ports:001C|001C]]
 
|[[:84PCE:Ports:001C|001C]]
 
|80
 
|80
|??
 
 
|Cannot change value
 
|Cannot change value
 
|-
 
|-
 
|[[:84PCE:Ports:0028|0028]]
 
|[[:84PCE:Ports:0028|0028]]
 
|
 
|
|FD
 
 
|Bit 1 is always 0, other bits latch value written
 
|Bit 1 is always 0, other bits latch value written
 
|-
 
|-
 
|[[:84PCE:Ports:0029|0029]]
 
|[[:84PCE:Ports:0029|0029]]
 
|00
 
|00
|01
 
 
|Bit 0 latches value written
 
|Bit 0 latches value written
 
|-
 
|-
 
|[[:84PCE:Ports:002A|002A]]
 
|[[:84PCE:Ports:002A|002A]]
 
|70
 
|70
|73
 
 
|Latches value written
 
|Latches value written
 
|-
 
|-
 
|[[:84PCE:Ports:002B|002B]]
 
|[[:84PCE:Ports:002B|002B]]
 
|FE
 
|FE
|FF
 
 
|Latches value written
 
|Latches value written
 
|-
 
|-
 
|[[:84PCE:Ports:002C|002C]]
 
|[[:84PCE:Ports:002C|002C]]
 
|
 
|
|FF
 
 
|Ports 002C-0031 latch value written
 
|Ports 002C-0031 latch value written
 
|-
 
|-
 
|[[:84PCE:Ports:0032|0032]]
 
|[[:84PCE:Ports:0032|0032]]
 
|
 
|
|07
 
 
|Latches value written
 
|Latches value written
 
|-
 
|-
 
|[[:84PCE:Ports:0033|0033]]
 
|[[:84PCE:Ports:0033|0033]]
 
|
 
|
|F1
 
 
|Latches value written
 
|Latches value written
 
|-
 
|-
 
|[[:84PCE:Ports:0034|0034]]
 
|[[:84PCE:Ports:0034|0034]]
 
|
 
|
|31
 
 
|Latches value written
 
|Latches value written
 
|-
 
|-
 
|[[:84PCE:Ports:0035|0035]]
 
|[[:84PCE:Ports:0035|0035]]
 
|
 
|
|3F
 
 
|Latches value written
 
|Latches value written
 
|-
 
|-
 
|[[:84PCE:Ports:0036|0036]]
 
|[[:84PCE:Ports:0036|0036]]
 
|
 
|
|FF
 
 
|Ports 0036-0039 latch value written
 
|Ports 0036-0039 latch value written
 
|-
 
|-
 
|}
 
|}

Revision as of 03:57, 6 August 2017


If a port is not listed; it indicates that writes have no effect and do not latch, and that reads are 0. Note that this may not be true one hundred percent.

0000 Range

Port    Default    Bits    Information   
0000 03 CPU Speed Control
0001 03 OS Timer Control
0002 Read only, value can change
0005 76 Set bit 5 to freeze, bit 6 affects backlight
0006 03 Display refresh
0007 B7 Latches values written
0008 7F Cannot change value
0009 37 Power control system
000A FD Latches value written
000C 00 Latches value written
000D FF Bit 0: Freeze if reset
Bit 1: Crash if reset
Bit 2: No apparent effect if reset
Bit 3: Reset to disable VRAM? Upon set, VRAM is garbage.
Bits [7:4]Possibly last value written
000E 0A Latches value written
000F 42 High nibble may be a status, low 2 bits latch value written
001C 80 Cannot change value
0028 Bit 1 is always 0, other bits latch value written
0029 00 Bit 0 latches value written
002A 70 Latches value written
002B FE Latches value written
002C Ports 002C-0031 latch value written
0032 Latches value written
0033 Latches value written
0034 Latches value written
0035 Latches value written
0036 Ports 0036-0039 latch value written