84PCE:Ports:6000

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Synopsis

Port Number: 6000-601F

Memory-mapped address: F10000

Function: Watchdog timer

This range of ports is a watchdog timer (appears to be model FTWDT010). Its primary feature is a 32-bit looping downward counter which can be set to either 32768Hz or the CPU frequency. It can also be used to reset the calculator or trigger a non-maskable interrupt (which typically will also reset the calculator). It is unknown whether it can trigger a maskable interrupt.

Registers

All registers are little-endian.

  • 6000-6003 (R):
    • 32-bit counter register.
  • 6004-6007 (R/W):
    • 32-bit load register. The counter is loaded with this value when it reaches 0 or the restart register is used.
  • 6008-6009 (W):
    • 16-bit restart register. When the value 5AB9h is written here, the counter is restarted. The bytes can be written individually.
  • 600C (R/W):
    • Bit 0: Timer enable. Set to make the counter count down.
    • Bit 1: System reset enable. Set to reboot the calculator when the counter reaches 0.
    • Bit 2: System reset interrupt enable. Set to trigger a non-maskable interrupt when the counter reaches 0.
    • Bit 3: External signal enable. Set to enable the external signal when the counter reaches 0 (this may have no effect).
    • Bit 4: Clock source. Set to 1 to use the 32768Hz clock, or 0 to use the CPU clock.
  • 6010 (R):
    • Status register. Bit 0 is set after the timer has reached 0, otherwise reset.
  • 6014 (W):
    • Status clear register. Write 1 to reset bit 0 of the status register.
  • 6018 (R/W):
    • 8-bit interrupt length register. Controls the amount of time an interrupt is signaled.
  • 601C-601F (R):
    • 32-bit revision register. Reads a constant 0x00010602, which corresponds to revision 1.6.2.