WikiTI - User contributions [en]

Category:83Plus:Ports:Unknown

2006-01-30T10:31:48Z

70.117.202.191: Removed excessive SEEMS and cleaned up a bit

[[Category:83Plus:Ports:By_Address|Unknown Ports]]

== Synopsis ==
There are several ports that have not yet been totally solved. Here is a list of them and what information is available.

===83+ & SE Calculator Ports===
'''Port 04:''' Writing:
* Bit 3: always 0, doesn't seem to have any effect
* Bit 4: always 1, doesn't seem to have any effect, guessing leftover from 83 code
* Bit 5: always 1, guessing same as 83
* Bit 6: default 1, guessing same as 83
* Bit 7: Voltage level at which port 02 bit 0 flips, default 0

===SE Calculator Ports Only===
'''Port 0B:'''
* Tied to the link assist on the SE calculators. Only written to in boot code where it receives B4.

'''Port 0C:'''
* Tied to the link assist on the SE calculators. Only written to in boot code where it receives B4.

'''Port 0E:'''
* Tied with swapping bank $4000. Before swapping pages this port should contain 00, otherwise data read from those pages may not be accurate.

'''Port 0F:'''
* Tied with swapping bank $8000. Before swapping pages this port should contain 00, otherwise data read from those pages may not be accurate.

'''Port 21:'''
* Although used as a hardware detection, it's more likely to be ram execution protection. See the talk page for more info. [[Talk:83Plus:Ports:21|Talk Page Port 21]]

'''Port 25:'''
* This port acts similarly to flash restriction port 22. Set to 16 by default. This is a [[Category:83Plus:Ports:By_Address:Protected|protected port]].

'''Port 26:'''
* This port acts similarly to flash restriction port 2223. Set to 32 by default. This is a [[Category:83Plus:Ports:By_Address:Protected|protected port]].

'''Port 2D:'''
* Only bits 0 and 1 can be altered, but no effect is apparent.

'''Port 2E:'''
* All bits can be altered but only 2 appear to have an effect. This port needs more information.

'''USB Ports:'''
* All information concerning the USB ports will be handled [[83Plus:OS:84_Plus_USB_Information|here]].

==Comments==
Other ports have unknown functions but are never written to, read from, or change in a significant way. Port 15 on the SE calculators has a value that does seem possible to change, but is not used directly. Other ports likely have no purpose at all.

There is still quite bit unknown about the hardware, however the remainder is less significant to or can not be used by the average coder.

== Credits and Contributions ==
* '''Tijl Coosemans'''
* '''Dan Englender'''
* '''James Montelongo'''
* '''Michael Vincent'''

Category:83Plus:Ports:Unknown

2006-01-29T12:19:46Z

70.117.202.191: Trying to make this a sub category

[[Category:83Plus:Ports:By_Address|Unknown Ports]]

== Synopsis ==
There are several ports that have not yet been totally solved. Here is a list of them and what information is available.

===83+ & SE Calculator Ports===
'''Port 04:''' Writing:
* Bit 3: always 0, doesn't seem to have any effect
* Bit 4: always 1, doesn't seem to have any effect, guessing leftover from 83 code
* Bit 5: always 1, guessing same as 83
* Bit 6: default 1, guessing same as 83
* Bit 7: Voltage level at which port 02 bit 0 flips, default 0

===SE Calculator Ports Only===
'''Port 0B:'''
* Seems to be tied to the link assist on the SE calculators. Only written to in boot code where it receives B4.

'''Port 0C:'''
* Seems to be tied to the link assist on the SE calculators. Only written to in boot code where it receives B4.

'''Port 0E:'''
* Seems to be tied with swapping bank $4000. Before swapping pages this port should contain 00, otherwise data read from pages may not be accurate. I have very little info on this port.

'''Port 0F:'''
* Seems to be tied with swapping bank $8000. Before swapping pages this port should contain 00, otherwise data read from pages may not be accurate. I have very little info on this port.

'''Port 21:'''
* Although used as a hardware detection, this seems to be ram execution protection. See the talk page for info. [[Talk:83Plus:Ports:21|Talk Page Port 21]]

'''Port 25:'''
* This port also seems to be flash restriction port like 22. Set to 16 by default.

'''Port 26:'''
* This port also seems to be flash restriction port like 23. Set to 32 by default.

'''Port 2D:'''
* Only bits 0 and 1 can be altered, doesn't seem to do anything.

'''Port 2E:'''
* All bits can be altered but only 2 seem to have an effect. This port needs more information.

'''USB Ports:'''
* All information about the USB ports are handled [[83Plus:OS:84_Plus_USB_Information|here]].

==Comments==
Other ports have unknown functions but are never written to, read from, or change in any way.

There is still quite bit unknown, but most seems to be insignificant.

== Credits and Contributions ==
* '''Tijl Coosemans'''
* '''Dan Englender'''
* '''James Montelongo'''
* '''Michael Vincent'''

Talk:83Plus:Ports:Unknown

2006-01-28T13:56:27Z

70.117.202.191:

I wanted this to be a sub catergory like protected ports, I'll let some else figure it out. - Jim e (to lazy to sign in)

83Plus:Ports:2F

2005-10-05T12:27:12Z

70.117.202.191: Rewrote with more accurate data, someone may want to rephrase a few things.

[[Category:83Plus:Ports:By Address|2F - LCD Wait Delay]]
[[Category:83Plus:Ports:By Name|LCD Wait Delay]]
{{SE-Only Port|07}}

== Synopsis ==
'''Port Number:''' 2Fh

'''Function:''' LCD Wait Delay

After every write to the LCD bit 1 of [[83Plus:Ports:02|port 2]] resets for a certain amount of time based on the current cpu speed and if the calculator is in hi speed mode. This port controls that amount time.

=== Read Values ===
* This port reads the last value written to it.

=== Write Values ===
* Bits 0-1 control the amount of tstates to wait when port 20 contains 1. The following values tell the number of tstates.
** 00 = 048 tstates
** 01 = 112 tstates
** 10 = 176 tstates
** 11 = 240 tstates

* Bits 2-4 control the amount of tstates to wait when port 20 contains 2. The following values tell the number of tstates.
** 000 = 048 tstates
** 001 = 112 tstates
** 010 = 176 tstates
** 011 = 240 tstates
** 100 = 304 tstates
** 101 = 368 tstates
** 110 = 432 tstates
** 111 = 496 tstates

* Bits 5-7 control the amount of tstates to wait when port 20 contains 3. The following values tell the number of tstates.
** 000 = 048 tstates
** 001 = 112 tstates
** 010 = 176 tstates
** 011 = 240 tstates
** 100 = 304 tstates
** 101 = 368 tstates
** 110 = 432 tstates
** 111 = 496 tstates

== Comments ==

This value really shouldn't be changed. TI-OS depends on this being set high enough to function for the LCD delay.

Also the 83+SE has this port set to 4A as default, the 84+(SE) has this port set to 4B as default.

== Credits and Contributions ==
* '''James Montelongo'''

83Plus:Ports:09

2005-08-21T13:05:55Z

70.117.202.191: Little more info

[[Category:83Plus:Ports:By_Address|09 - Link Assist Status]] [[Category:83Plus:Ports:By_Name|Link Assist Status]]
== Synopsis ==
'''Port Number:''' 09h

'''Function:''' Link Assist Status

This port gives information on the status of the hardware link assist.

=== Read Values ===
* Bit 0: Set if an interrupt was generated by receiving a byte.
* Bit 1: Set if an interrupt was generated when a byte can be sent.
* Bit 2: Set if an interrupt was generated due to an error in transmission.
* Bit 3: Set if the assist is currently receiving data
* Bit 4: Set if the assist has read a complete byte (which can be read from [[83Plus:Ports:0A|port 0A]])
* Bit 5: Set if the assist is ready to write data (via [[83Plus:Ports:0D|port 0D]])
* Bit 6: Set if there was an error during transmission
* Bit 7: Set if the link assist is currently sending a byte.

=== Write Values ===
''None''

== Comments ==
This port only exists on the 83+ SE and the 84+.

== Credits and Contributions ==
* '''Michael Vincent:''' Original documentation of the link assist

83Plus:Ports:08

2005-08-21T13:02:45Z

70.117.202.191: More info

[[Category:83Plus:Ports:By_Address|08 - Link Assist Enable]] [[Category:83Plus:Ports:By_Name|Link Assist Enable]]
== Synopsis ==
'''Port Number:''' 08h

'''Function:''' Link Assist Enable

This port controls whether the hardware link assist is enabled.

=== Read Values ===
* Bit 1: 1 if link assist will generate an interrupt when a byte is received. (Link assist must be enabled)
* Bit 2: 1 if link assist will generate an interrupt when a byte can be sent. (Link assist must be enabled)
* Bit 3: 1 if link assist will generate an interrupt when an error has occurred. (Link assist must be enabled)
* Bit 7: 1 if the link assist is disabled.

=== Write Values ===
* Bit 1: Set to generate an interrupt when link assist receives a byte. (Link assist must be enabled)
* Bit 2: Set to generate an interrupt when link assist is able to send byte. (Link assist must be enabled)
* Bit 3: Set to generate an interrupt when an error occurs. (Link assist must be enabled)
* Bit 7: 1 to disable the link assist.

== Comments ==
This port only exists on the 83+ SE and the 84+.

Programs which directly control the link port should disable the hardware assist.

The timeout for the link assist is ~2 seconds.

===Interrupts===
Link Assist hardware can generate an interrupt when a byte is received, when a byte can be sent or when an error in transmission occurs.

To enable an interrupt when a byte is received write 01 to port 08. When a byte received and an interrupt is generated bit 0 of port 9 is set. Like all interrupts this one needs to be acknowledged, do this by reading the byte from port 0A.

To enable an interrupt when a byte can be sent write 2 to port 08. When the the link assist is not busy it will generate an interrupt so you can send data. Bit 1 of port 9 is set when this interrupt generates. You acknowledge this interrupt by writing to port 0D.

To enable an interrupt when an error occurs have bit 2 set when you write to port 08. It is not necessary to have the the other link assist interrupts enabled but you can. When this interrupt generates bit 2 of port 9 is set, and it is acknowledged by reading port 9.

The biggest benefit from the link assist interrupts is that no time must wasted waiting, it could take millisecond to send or receive a byte. With interrupts that time can be put to more useful code. I don't believe that you should have both the send and receive interrupts enabled at the same. But really communication would dictate who is sending and receiving. Remember that TI-OS does not seem to handle these interrupts, disable them when your through.

== Credits and Contributions ==
* '''Michael Vincent:''' Original documentation of the link assist
* '''James Montelongo:''' Interrupt information