WikiTI - User contributions [en]

User:Fundudeone

2025-08-11T02:09:38Z

Dr. D'nar: Creating user page for new user.

I enjoy programming for the TI84+ CE as a hobby, and I am """technically""" a toolchain contributor. I'm hoping to document 84PCE ports that are writable but currently have no known function, specifically those related to the serial flash chip.

User talk:Fundudeone

2025-08-11T02:09:38Z

Dr. D'nar: Welcome!

'''Welcome to ''WikiTI''!'''
We hope you will contribute much and well.
You will probably want to read the [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents help pages].
Again, welcome and have fun! [[User:Dr. D'nar|Dr. D'nar]] ([[User talk:Dr. D'nar|talk]]) 19:09, 10 August 2025 (PDT)

User talk:Thecaticorn01

2025-04-10T03:54:40Z

Dr. D'nar: Welcome!

User:Thecaticorn01

2025-04-10T03:54:39Z

Dr. D'nar: Creating user page for new user.

Hello!

I am a high school student with moderate programming experience in Java, Python, HTML/CSS/JS, and the TI-BASIC programming languages (both the version for the TI-84+CE and for the TI-nSpire CX series).

I am currently teaching myself ez80 assembly so I can make calculator programs!

I have a TI-84 Plus Silver Edition (my first calculator!), a TI-84 Plus CE (which I mostly use for gaming and programming), and a TI-nSpire CX II CAS (which I use for school).

User:Tortuguese

2025-04-10T03:51:38Z

Dr. D'nar: Creating user page for new user.

Programming TI Calculators for 6-7 years. Just started with assembly, trying to clean-up the Syscalls and other information for future programmers!

User talk:Tortuguese

2025-04-10T03:51:38Z

Dr. D'nar: Welcome!

User:Tanja158

2025-04-10T03:46:52Z

Dr. D'nar: Creating user page for new user.

Student of IT; Interested in Programming and getting to know new languages

User talk:Tanja158

2025-04-10T03:46:52Z

Dr. D'nar: Welcome!

User talk:HackerDaGreat57

2025-04-10T03:45:55Z

Dr. D'nar: Welcome!

User:HackerDaGreat57

2025-04-10T03:45:55Z

Dr. D'nar: Creating user page for new user.

I'm a high school sophomore who is interested in TI-84+SE and RP2040 programming. I consider writing assembly code an art form and love to learn all about development platforms like TI calculators and microcontrollers, and I hope I can design my own CPU one day in SystemVerilog.

User talk:HeronErin

2025-04-10T03:45:25Z

Dr. D'nar: Welcome!

User:HeronErin

2025-04-10T03:45:24Z

Dr. D'nar: Creating user page for new user.

I am a TI83+ / TI84+ enthusiast. Love learning things about calculators, and have been hacking at them for years.

User:Olivebranch

2025-04-10T03:44:33Z

Dr. D'nar: Creating user page for new user.

A couple of months ago, around November 2023, I got interested in writing code for my Ti-83 Plus. So I got myself a link cable and a copy of brass, and the rest is history. I'm currently somewhat adept at writing z80 assembly and very good at Python. I am also working on a Ti-83 Plus emulator for fun, which funnily enough happens to be the reason I found my way to this website while looking for info on ports. I plan on eventually forking KnightOS or using the kernel for my own OS, or something along those lines.

User talk:Olivebranch

2025-04-10T03:44:33Z

Dr. D'nar: Welcome!

User:Clevor

2025-04-10T03:43:52Z

Dr. D'nar: Creating user page for new user.

Got a calculator in 6th grade, and I originally wanted a TI-Nspire CX II. However, they were sold out at the Walmart my mom and I went to. I got a Ti-84 Plus CE revision M there, and I used it a lot. I made a math menu helper thing tool called Mather, which was just yet another math menu equation thing. In 8th grade, I found a TI-84 Plus CE revision I in a lost and found drawer. I wanted a TI-84 Plus, so I traded my first CE with one of my cousins, who had an 84+ revision AB. I kept the revision I CE because I was able to install BOS on it, and I did once. In July of 2023, I bought a TI-Nspire with Touchpad. Just for Ndless, I bought a TI-Nspire CX II CAS the next month. I wanted to see the 68k series, so I bought a TI-89 Titanium in October. Unfortunately, it didn't respond to keypresses, unless via a genetated interrupt. After that, I bought a Voyage 200, which had abour 6 dead columns in the Ebay listing. Sometimes, it would change from 3 to 2 or 1 dead columns, which was strange. There was always 1 specific column that always stayed dead, no matter what. The day after I got my Voyage 200, my Geometry teacher got me her old TI-83 Plus. It didn't work. I don't have much of a plan on what [TI] calculator to buy next, as I am comfortable with what I have. When the Zero Calculator comes out, I may or may not buy it.

My eventual goal is to have 1 of every calculator model. I am not going to buy a second copy of a calculator, unless it was given to me as a gift. I also want a single prototype calculator, which doesn't count towards the previous "rule".

User talk:Clevor

2025-04-10T03:43:52Z

Dr. D'nar: Welcome!

User:SJRw

2022-08-26T18:20:32Z

Dr. D'nar: Creating user page for new user.

Heath Wang is my calculator “real name”, I have no relation to other incidental Heath Wangs that exist. I am sJRw on cemetech.net

User talk:SJRw

2022-08-26T18:20:32Z

Dr. D'nar: Welcome!

User talk:TIny Hacker

2022-08-26T18:15:49Z

Dr. D'nar: Welcome!

User:TIny Hacker

2022-08-26T18:15:48Z

Dr. D'nar: Creating user page for new user.

Hi, I'm TIny_Hacker and I program calculators! This is my WikiTI page. There's not really anything else to say here.

84PCE:Ports:0009

2022-05-25T06:02:23Z

Dr. D'nar: /* Bit [2] */ LCD /RESET

[[Category:84PCE:Ports:By_Address|0009 - GPIO A OUT]] [[Category:84PCE:Ports:By_Name|GPIO A OUT]]
== Synopsis ==
'''Port Number:''' 0009

'''Function:''' GPIO A Output

== Details ==

These GPIOs appear to be connected to power control.

=== Bits [1:0] ===
Latches value written, no apparent effect.

=== Bit [2] ===
Likely connected to the LCD's reset line, which is active low. After being set, the LCD must be given a sequence of initialization commands before it can display an image again.

=== Bit [3] ===
Latches value written, no apparent effect.

=== Bit [4] ===
SPI slave select - reset to communicate with the LCD, set to communicate with the Python coprocessor.

=== Bits [7:5] ===
Latches value written, no apparent effect.

User:Sue Doenim

2022-05-01T20:16:20Z

Dr. D'nar: Creating user page for new user.

My programming career began in the humble TI-Basic program editor.

User talk:Sue Doenim

2022-05-01T20:16:20Z

Dr. D'nar: Welcome!

User:Mrwompwomp

2022-05-01T20:15:12Z

Dr. D'nar: Creating user page for new user.

I am a calculator enthusiast and cemetech member. You can find me under a heaping pile of prototypes.

User talk:Mrwompwomp

2022-05-01T20:15:12Z

Dr. D'nar: Welcome!

User:MicahSuess

2022-05-01T20:13:59Z

Dr. D'nar: Creating user page for new user.

Electrical engineering and programming hobbyist. Experience with arduino micro controllers, and TI-84 Plus CE.

User talk:MicahSuess

2022-05-01T20:13:59Z

Dr. D'nar: Welcome!

User talk:IPhoenix

2022-05-01T20:12:50Z

Dr. D'nar: Welcome!

User:IPhoenix

2022-05-01T20:12:49Z

Dr. D'nar: Creating user page for new user.

I wonder how hard it is to reach ten words.

84PCE:Wait States

2022-04-24T19:12:12Z

Dr. D'nar: /* Wait State Layout */ You can map up to 12 MB of serial flash

[[Category:84PCE:General_Hardware_Information|Wait States]]
== Synopsis ==
The eZ80 processor is able to perform a memory access in a single cycle. However, on the TI-84+CE, accesses will actually take longer due to wait states. For example, a read from RAM will take 4 cycles, because it has 3 wait states. The wait states for parallel Flash accesses can be customized, but it is unknown whether that is the case for other memory regions or for the newer serial flash.

== Flash Access Wait States ==

=== Parallel Flash ===
Calculators produced prior to revision M use a parallel flash chip. These chips are limited to a maximum read rate under 20 MHz, necessitating at least 1 wait state for the ASIC's faster 48 MHz clock. The ASIC's internal memory mapping hardware adds a minimum of 5 wait states just to ferry the request to the flash chip and the response back to the CPU, but additional external wait states are required for the flash chip to make its reply. See [[84PCE:Ports:1005]] for more information.

=== Serial Flash ===
Calculators produced starting in 2019 with revision M no longer use a parallel flash chip, but instead an SPI flash chip. This flash chip needs much longer to initially retrieve data from a random address, but can stream sequential data at a reasonable rate. A new ASIC design takes advantage of this capability by adding a cache between the flash chip and CPU.

According to tests performed by [[User:Jacobly|Jacobly]], the cache is 8 K in size, structured as a 2-way set associative cache with 128 sets of 32 bytes chosen by address bits 5-11. A fetch from the same cache line as previously accessed costs 1 wait state (so the read takes a total of 2 cycles), a fetch from a different cache line costs 2 wait states, and a cache miss costs 194-200 wait states.

Code execution from flash displays high locality of reference, so amortized performance should be reasonably good, although the 200 cycle penalty for a cache miss probably hurts a fair bit. For flash-resident data files, programmers should try to organize them to keep related data together to maximize cache utilization. A good access pattern can make accessing data in flash twice as fast as getting it from RAM, while a bad pattern can make it substantially worse than even pulling it from the old parallel flash.

== LCD DMA ==
The LCD controller uses Direct Memory Access to retrieve the pixels from RAM. However, since the CPU and the LCD controller cannot access RAM at the same time, there are some waitstates caused asynchronously by the DMA during RAM accesses. The rate of waitstates caused by the DMA appears to be directly proportional to the rate of data being sent to the screen, so lower bit-per-pixel modes will reduce the general performance hit.

== Wait State Layout ==
{|-
|Address Range   
|Read   
|Write   
|Description   
|-
|000000-3FFFFF
|5+
|Crash
|[[84PCE:Ports:1000|Parallel flash]]: Wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. The OS sets a total of 9 wait states.
|-
|000000-3FFFFF
|1-200
|Crash
|[[84PCE:OS:Serial_Flash_Commands|Serial flash:]] See above discussion.
|-
|400000-7FFFFF
|257
|Crash
|Parallel flash: Unmapped address space. Can be mapped to Flash using [[:84PCE:Ports:1002|1002]], after which Flash wait states are active.
|-
|400000-BFFFFF
|1-200
|Crash
|Serial flash: Flash mirrors. Up to 12 MB of total flash can be mapped using [[:84PCE:Ports:1000|182E]].
|-
|800000-CFFFFF
|257
|257
|Parallel flash: Unmapped address space.
|-
|C00000-CFFFFF
|1
|1
|Serial flash: Unmapped address space.
|-
|D00000-D3FFFF
|3
|1
|RAM
|-
|D40000-D657FF
|3
|1
|VRAM
|-
|D65800-D72BFF
|3
|1
|Unmapped address space. Reads garbage.
|-
|D72C00-D7FFFF
|3
|1
|Unmapped address space. Reads garbage (revisions up to at least C) or mirror of D52C00-D5FFFF (at least I-S).
|-
|D80000-DFFFFF
|3
|1
|Mirror of D00000-D7FFFF
|-
|Not mapped
|1
|1
|Port range [[:84PCE:Ports:0000|0000]] (mirrored every 0100 bytes)
|-
|E00000-E0FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:1000|1000]] (mirrored every 0100 bytes)
|-
|E10000-E1FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:2000|2000]] (mirrored every 0100 bytes)
|-
|E20000-E2FFFF
|3

9-12

6-8

5-6

4-5
|3

9-12

6-8

5-6

4-5
|Memory-mapped port range [[:84PCE:Ports:3000|3000]] (mirrored every 0200 bytes)

Extra cycles if bit 7 ''or'' 8 of the address is set, when cpu is running at 48 MHz.

Same at 24 MHz.

Same at 12 MHz.

Same at 6 MHz.
|-
|E30000-E3FFFF
|2

2

2

2

2

3

1

1

1

1
|1

20-21/22

15/13

11

9

3

15-16/13

12/10

10/8

8
|Memory-mapped port range [[:84PCE:Ports:4000|4000]] (mirrored every 1000 bytes)

Special timing for 4000-400F & 4018-401B (pre-M/M+) at 48 MHz

Same at 24 MHz

Same at 12 MHz

Same at 6 MHz

Special timing for 4200-43FF (any CPU speed)

Special timing for 4C00-4DFF (pre-M/M+) at 48 MHz

Same at 24 MHz

Same at 12 MHz

Same at 6 MHz
|-
|E40000-EFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-
|F00000-F0FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:5000|5000]] (mirrored every 0100 bytes)
|-
|F10000-F1FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:6000|6000]] (mirrored every 0020 bytes)
|-
|F20000-F2FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:7000|7000]] (mirrored every 0100 bytes)
|-
|F30000-F3FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:8000|8000]] (mirrored every 0080 bytes)
|-
|F40000-F4FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:9000|9000]] (mirrored every 1000 bytes, possibly protected port range)
|-
|F50000-F5FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:A000|A000]] (mirrored every 0080 bytes)
|-
|F60000-F6FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:B000|B000]] (mirrored every 1000 bytes)
|-
|F70000-F7FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:C000|C000]] (mirrored every 0100 bytes)
|-
|F80000-F8FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:D000|D000]] (mirrored every 0080 bytes)
|-
|F90000-F9FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:E000|E000]] (mirrored every 0080 bytes)
|-
|FA0000-FAFFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:F000|F000]] (mirrored every 0100 bytes)
|-
|FB0000-FEFFFF
|2
|2
|Unmapped port range (reads all zeros)
|-
|FF0000-FFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-}

83Plus:Overclocking

2020-05-08T03:36:48Z

Dr. D'nar: Ugh, fix characters AGAIN

[[Category:83Plus:General Hardware Information|Overclocking]]
[[Category:84PCSE:General Hardware Information|Overclocking]]

The TI-83+SE, TI-84+, TI-84+SE, and TI-84+CSE can all be overclocked. The TI-83+SE had special solder pads to enable overclocking, but the TI-84+ series lacks them.

[[File:TA3 ASIC overclock.jpg|350px|thumb|right|Image of the TA3 ASIC highlighting the relevant pins. Note the silk-screened pin 1 label and the filled circle on the upper-left of the ASIC.]]

The TI-84+CSE and older TI-84+/SEs use the TA3 ASIC (port 15 reads 45h), pictured on the right. Pins 67-72 on the TA3 connect to an external RC tank circuit. The calculators have 4 CPU speed modes, which were originally supposed to be 6, 15, 20, and 25 MHz; production calculators only have 6 and 15 MHz modes. The four red pins correspond to the four CPU speed modes.

To enable speeds 02 and 03 on the TA3, add resistors on pins 70 and 71. The calculator seems unstable above 22 MHz, which suggests that TI didn't implement the 20 MHz mode due to resistors not being accurate enough (some calcs might get a particularly bad resistor and end up being more like 23 MHz for the resistor value that should give 20 MHz). The TA1 ASIC is a reduced pin count design and appears to lack the pins for the 02 and 03 CPU modes.

[[File:TA1 ASIC overclock.jpg|350px|thumb|right|Image of the TA1 ASIC highlighting the relevant pins. Note the silk-screened pin 51 label.]]

Each successive CPU speed mode enables more resistors in parallel. In mode 0, only R08D is used; in mode 1, R07D is in parallel with R08D. On my (DrDnar's) calculators, I get R08D ≈ 1.8 kΩ and R07D ≈ 1.2 kΩ. To overclock CPU speed 1 to ≈ 20.4 MHz, replace R07D with an 820 Ω resistor. 20 MHz is pushing the limits of what the flash chip is spec'd for, so consider instead 910 Ω for ≈ 19 MHz, or 1 kΩ for ≈ 18 MHz, which should hopefully be safe for all calculators.

However, a much easier---though less precise---method is to adjust R07D with a pencil. The graphite marks left by pencils are actually conductive, and it turns out that HB pencil marks are in the right range for adjusting the resistor's value. By drawing a really heavy mark over the face of the whole resistor, you can pull down the resistance enough to get 18-19 or so MHz. It's also possible that a different weight lead like 9B might be even more conductive, allowing even faster speeds, and you can always smudge the graphite off with your finger if the calculator proves unstable.

83Plus:Overclocking

2020-05-08T03:19:04Z

Dr. D'nar: Pencils: The great makeshift trim pot

[[Category:83Plus:General Hardware Information|Overclocking]]
[[Category:84PCSE:General Hardware Information|Overclocking]]

The TI-83+SE, TI-84+, TI-84+SE, and TI-84+CSE can all be overclocked. The TI-83+SE had special solder pads to enable overclocking, but the TI-84+ series lacks them.

[[File:TA3 ASIC overclock.jpg|350px|thumb|right|Image of the TA3 ASIC highlighting the relevant pins. Note the silk-screened pin 1 label and the filled circle on the upper-left of the ASIC.]]

The TI-84+CSE and older TI-84+/SEs use the TA3 ASIC (port 15 reads 45h), pictured on the right. Pins 67-72 on the TA3 connect to an external RC tank circuit. The calculators have 4 CPU speed modes, which were originally supposed to be 6, 15, 20, and 25 MHz; production calculators only have 6 and 15 MHz modes. The four red pins correspond to the four CPU speed modes.

To enable speeds 02 and 03 on the TA3, add resistors on pins 70 and 71. The calculator seems unstable above 22 MHz, which suggests that TI didn't implement the 20 MHz mode due to resistors not being accurate enough (some calcs might get a particularly bad resistor and end up being more like 23 MHz for the resistor value that should give 20 MHz). The TA1 ASIC is a reduced pin count design and appears to lack the pins for the 02 and 03 CPU modes.

[[File:TA1 ASIC overclock.jpg|350px|thumb|right|Image of the TA1 ASIC highlighting the relevant pins. Note the silk-screened pin 51 label.]]

Each successive CPU speed mode enables more resistors in parallel. In mode 0, only R08D is used; in mode 1, R07D is in parallel with R08D. On my (DrDnar's) calculators, I get R08D ≈ 1.8 k? and R07D ≈ 1.2 k?. To overclock CPU speed 1 to ≈ 20.4 MHz, replace R07D with an 820 ? resistor. 20 MHz is pushing the limits of what the flash chip is spec'd for, so consider instead 910 ? for ≈ 19 MHz, or 1 k? for ≈ 18 MHz, which should hopefully be safe for all calculators.

However, a much easier---though less precise---method is to adjust R07D with a pencil. The graphite marks left by pencils are actually conductive, and it turns out that HB pencil marks are in the right range for adjusting the resistor's value. By drawing a really heavy mark over the face of the whole resistor, you can pull down the resistance enough to get 18-19 or so MHz. It's also possible that a different weight lead like 9B might be even more conductive, allowing even faster speeds, and you can always smudge the graphite off with your finger if the calculator proves unstable.

User:Wilkgr

2020-05-08T01:49:26Z

Dr. D'nar: Creating user page for new user.

Hi! I'm not sure what to exactly but in a biography. I'm a first year uni student studying engineering. I'm no longer allowed to use graphing calculators for exams (I was allowed at school) so I thought now is as good of a time as any to hack on them. I'm not particularly experienced with them. I have two TI-84+, one of which is broken, and a TI-Nspire CX CAS.

User talk:Wilkgr

2020-05-08T01:49:26Z

Dr. D'nar: Welcome!

83Plus:Overclocking

2020-05-08T00:14:26Z

Dr. D'nar: Hopefully fix characters

[[Category:83Plus:General Hardware Information|Overclocking]]
[[Category:84PCSE:General Hardware Information|Overclocking]]

The TI-83+SE, TI-84+, TI-84+SE, and TI-84+CSE can all be overclocked. The TI-83+SE had special solder pads to enable overclocking, but the TI-84+ series lacks them.

[[File:TA3 ASIC overclock.jpg|350px|thumb|right|Image of the TA3 ASIC highlighting the relevant pins. Note the silk-screened pin 1 label and the filled circle on the upper-left of the ASIC.]]

The TI-84+CSE and older TI-84+/SEs use the TA3 ASIC (port 15 reads 45h), pictured on the right. Pins 67-72 on the TA3 connect to an external RC tank circuit. The calculators have 4 CPU speed modes, which were originally supposed to be 6, 15, 20, and 25 MHz; production calculators only have 6 and 15 MHz modes. The four red pins correspond to the four CPU speed modes.

To enable speeds 02 and 03 on the TA3, add resistors on pins 70 and 71. The calculator seems unstable above 22 MHz, which suggests that TI didn't implement the 20 MHz mode due to resistors not being accurate enough (some calcs might get a particularly bad resistor and end up being more like 23 MHz for the resistor value that should give 20 MHz). The TA1 ASIC is a reduced pin count design and appears to lack the pins for the 02 and 03 CPU modes.

[[File:TA1 ASIC overclock.jpg|350px|thumb|right|Image of the TA1 ASIC highlighting the relevant pins. Note the silk-screened pin 51 label.]]

Each successive CPU speed mode enables more resistors in parallel. In mode 0, only R08D is used; in mode 1, R07D is in parallel with R08D. On my (DrDnar's) calculators, I get R08D ≈ 1.8 k? and R07D ≈ 1.2 k?. To overclock CPU speed 1 to ≈ 20.4 MHz, replace R07D with an 820 ? resistor. 20 MHz is pushing the limits of what the flash chip is spec'd for, so consider instead 910 ? for ≈ 19 MHz, or 1 k? for ≈ 18 MHz, which should hopefully be safe for all calculators.

83Plus:Overclocking

2020-05-08T00:11:51Z

Dr. D'nar: Add specifics for overclocking

[[Category:83Plus:General Hardware Information|Overclocking]]
[[Category:84PCSE:General Hardware Information|Overclocking]]

The TI-83+SE, TI-84+, TI-84+SE, and TI-84+CSE can all be overclocked. The TI-83+SE had special solder pads to enable overclocking, but the TI-84+ series lacks them.

[[File:TA3 ASIC overclock.jpg|350px|thumb|right|Image of the TA3 ASIC highlighting the relevant pins. Note the silk-screened pin 1 label and the filled circle on the upper-left of the ASIC.]]

The TI-84+CSE and older TI-84+/SEs use the TA3 ASIC (port 15 reads 45h), pictured on the right. Pins 67-72 on the TA3 connect to an external RC tank circuit. The calculators have 4 CPU speed modes, which were originally supposed to be 6, 15, 20, and 25 MHz; production calculators only have 6 and 15 MHz modes. The four red pins correspond to the four CPU speed modes.

To enable speeds 02 and 03 on the TA3, add resistors on pins 70 and 71. The calculator seems unstable above 22 MHz, which suggests that TI didn't implement the 20 MHz mode due to resistors not being accurate enough (some calcs might get a particularly bad resistor and end up being more like 23 MHz for the resistor value that should give 20 MHz). The TA1 ASIC is a reduced pin count design and appears to lack the pins for the 02 and 03 CPU modes.

[[File:TA1 ASIC overclock.jpg|350px|thumb|right|Image of the TA1 ASIC highlighting the relevant pins. Note the silk-screened pin 51 label.]]

Each successive CPU speed mode enables more resistors in parallel. In mode 0, only R08D is used; in mode 1, R07D is in parallel with R08D. On my (DrDnar's) calculators, I get R08D ? 1.8 k? and R07D ? 1.2 k?. To overclock CPU speed 1 to ? 20.4 MHz, replace R07D with an 820 ? resistor. 20 MHz is pushing the limits of what the flash chip is spec'd for, so consider instead 910 ? for ? 19 MHz, or 1 k? for ? 18 MHz, which should hopefully be safe for all calculators.

83Plus:Overclocking

2020-05-06T23:03:24Z

Dr. D'nar: Add information for the TA1 ASIC.

File:TA1 ASIC overclock.jpg

2020-05-06T22:36:43Z

Dr. D'nar: This file highlights the relevant pins for overclocking the TA1 ASIC used in newer TI-84+/SEs.

This file highlights the relevant pins for overclocking the TA1 ASIC used in newer TI-84+/SEs.

84PCE:Wait States

2020-04-18T18:47:04Z

Dr. D'nar: Serial flash mirrors

[[Category:84PCE:General_Hardware_Information|Wait States]]
== Synopsis ==
The eZ80 processor is able to perform a memory access in a single cycle. However, on the TI-84+CE, accesses will actually take longer due to wait states. For example, a read from RAM will take 4 cycles, because it has 3 wait states. The wait states for parallel Flash accesses can be customized, but it is unknown whether that is the case for other memory regions or for the newer serial flash.

== Flash Access Wait States ==

=== Parallel Flash ===
Calculators produced prior to revision M use a parallel flash chip. These chips are limited to a maximum read rate under 20 MHz, necessitating at least 1 wait state for the ASIC's faster 48 MHz clock. The ASIC's internal memory mapping hardware adds a minimum of 5 wait states just to ferry the request to the flash chip and the response back to the CPU, but additional external wait states are required for the flash chip to make its reply. See [[84PCE:Ports:1005]] for more information.

=== Serial Flash ===
Calculators produced starting in 2019 with revision M no longer use a parallel flash chip, but instead an SPI flash chip. This flash chip needs much longer to initially retrieve data from a random address, but can stream sequential data at a reasonable rate. A new ASIC design takes advantage of this capability by adding a cache between the flash chip and CPU.

According to tests performed by [[User:Jacobly|Jacobly]], the cache is 8 K in size, structured as a 2-way set associative cache with 128 sets of 32 bytes chosen by address bits 5-11. A fetch from the same cache line as previously accessed costs 1 wait state (so the read takes a total of 2 cycles), a fetch from a different cache line costs 2 wait states, and a cache miss costs 194-200 wait states.

Code execution from flash displays high locality of reference, so amortized performance should be reasonably good, although the 200 cycle penalty for a cache miss probably hurts a fair bit. For flash-resident data files, programmers should try to organize them to keep related data together to maximize cache utilization. A good access pattern can make accessing data in flash twice as fast as getting it from RAM, while a bad pattern can make it substantially worse than even pulling it from the old parallel flash.

== LCD DMA ==
The LCD controller uses Direct Memory Access to retrieve the pixels from RAM. However, since the CPU and the LCD controller cannot access RAM at the same time, there are some waitstates caused asynchronously by the DMA during RAM accesses. The rate of waitstates caused by the DMA appears to be directly proportional to the rate of data being sent to the screen, so lower bit-per-pixel modes will reduce the general performance hit.

== Wait State Layout ==
{|-
|Address Range   
|Read   
|Write   
|Description   
|-
|000000-3FFFFF
|5+
|Crash
|[[84PCE:Ports:1000|Parallel flash]]: Wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. The OS sets a total of 9 wait states.
|-
|000000-3FFFFF
|1-200
|Crash
|[[84PCE:OS:Serial_Flash_Commands|Serial flash:]] See above discussion.
|-
|400000-7FFFFF
|257
|Crash
|Parallel flash: Unmapped address space. Can be mapped to Flash using [[:84PCE:Ports:1002|1002]], after which Flash wait states are active.
|-
|400000-BFFFFF
|1-200
|Crash
|Serial flash: Flash mirrors. Appears to be subject to flash cache timing as discussed above
|-
|800000-CFFFFF
|257
|257
|Parallel flash: Unmapped address space.
|-
|C00000-CFFFFF
|1
|1
|Serial flash: Unmapped address space.
|-
|D00000-D3FFFF
|3
|1
|RAM
|-
|D40000-D657FF
|3
|1
|VRAM
|-
|D65800-D7FFFF
|3
|1
|Unmapped address space. Reads garbage.
|-
|D80000-DFFFFF
|3
|1
|Mirror of D00000-D7FFFF
|-
|Not mapped
|1
|1
|Port range [[:84PCE:Ports:0000|0000]] (mirrored every 0100 bytes)
|-
|E00000-E0FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:1000|1000]] (mirrored every 0100 bytes)
|-
|E10000-E1FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:2000|2000]] (mirrored every 0100 bytes)
|-
|E20000-E2FFFF
|3

9-12

6-8

5-6

4-5
|3

9-12

6-8

5-6

4-5
|Memory-mapped port range [[:84PCE:Ports:3000|3000]] (mirrored every 0200 bytes)

Extra cycles if bit 7 ''or'' 8 of the address is set, when cpu is running at 48Mhz.

Same at 24Mhz.

Same at 12Mhz.

Same at 6Mhz.
|-
|E30000-E3FFFF
|2
|1
|Memory-mapped port range [[:84PCE:Ports:4000|4000]] (mirrored every 1000 bytes)
|-
|E40000-EFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-
|F00000-F0FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:5000|5000]] (mirrored every 0100 bytes)
|-
|F10000-F1FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:6000|6000]] (mirrored every 0020 bytes)
|-
|F20000-F2FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:7000|7000]] (mirrored every 0100 bytes)
|-
|F30000-F3FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:8000|8000]] (mirrored every 0080 bytes)
|-
|F40000-F4FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:9000|9000]] (mirrored every 1000 bytes, possibly protected port range)
|-
|F50000-F5FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:A000|A000]] (mirrored every 0080 bytes)
|-
|F60000-F6FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:B000|B000]] (mirrored every 1000 bytes)
|-
|F70000-F7FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:C000|C000]] (mirrored every 0100 bytes)
|-
|F80000-F8FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:D000|D000]] (mirrored every 0080 bytes)
|-
|F90000-F9FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:E000|E000]] (mirrored every 0080 bytes)
|-
|FA0000-FAFFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:F000|F000]] (reads all zeros)
|-
|FB0000-FEFFFF
|2
|2
|Unmapped port range (reads all zeros)
|-
|FF0000-FFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-}

User:ItsBrando

2020-04-18T16:32:56Z

Dr. D'nar: Creating user page for new user.

z80, eZ80, and C programmer for TI-84 and TI-84PCE

User talk:ItsBrando

2020-04-18T16:32:56Z

Dr. D'nar: Welcome!

84PCE:Wait States

2020-04-18T16:28:52Z

Dr. D'nar: Update for serial flash

[[Category:84PCE:General_Hardware_Information|Wait States]]
== Synopsis ==
The eZ80 processor is able to perform a memory access in a single cycle. However, on the TI-84+CE, accesses will actually take longer due to wait states. For example, a read from RAM will take 4 cycles, because it has 3 wait states. The wait states for parallel Flash accesses can be customized, but it is unknown whether that is the case for other memory regions or for the newer serial flash.

== Flash Access Wait States ==

=== Parallel Flash ===
Calculators produced prior to revision M use a parallel flash chip. These chips are limited to a maximum read rate under 20 MHz, necessitating at least 1 wait state for the ASIC's faster 48 MHz clock. The ASIC's internal memory mapping hardware adds a minimum of 5 wait states just to ferry the request to the flash chip and the response back to the CPU, but additional external wait states are required for the flash chip to make its reply. See [[84PCE:Ports:1005]] for more information.

=== Serial Flash ===
Calculators produced starting in 2019 with revision M no longer use a parallel flash chip, but instead an SPI flash chip. This flash chip needs much longer to initially retrieve data from a random address, but can stream sequential data at a reasonable rate. A new ASIC design takes advantage of this capability by adding a cache between the flash chip and CPU.

According to tests performed by [[User:Jacobly|Jacobly]], the cache is 8 K in size, structured as a 2-way set associative cache with 128 sets of 32 bytes chosen by address bits 5-11. A fetch from the same cache line as previously accessed costs 1 wait state (so the read takes a total of 2 cycles), a fetch from a different cache line costs 2 wait states, and a cache miss costs 194-200 wait states.

Code execution from flash displays high locality of reference, so amortized performance should be reasonably good, although the 200 cycle penalty for a cache miss probably hurts a fair bit. For flash-resident data files, programmers should try to organize them to keep related data together to maximize cache utilization. A good access pattern can make accessing data in flash twice as fast as getting it from RAM, while a bad pattern can make it substantially worse than even pulling it from the old parallel flash.

== LCD DMA ==
The LCD controller uses Direct Memory Access to retrieve the pixels from RAM. However, since the CPU and the LCD controller cannot access RAM at the same time, there are some waitstates caused asynchronously by the DMA during RAM accesses. The rate of waitstates caused by the DMA appears to be directly proportional to the rate of data being sent to the screen, so lower bit-per-pixel modes will reduce the general performance hit.

== Wait State Layout ==
{|-
|Address Range   
|Read   
|Write   
|Description   
|-
|000000-3FFFFF
|5+
|Crash
|[[84PCE:Ports:1000|Parallel flash]]: Wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. The OS sets a total of 9 wait states.
|-
|000000-3FFFFF
|1-200
|Crash
|[[84PCE:OS:Serial_Flash_Commands|Serial flash:]] See above discussion.
|-
|400000-7FFFFF
|257
|Crash
|Parallel flash: Unmapped address space. Can be mapped to Flash using [[:84PCE:Ports:1002|1002]], after which Flash wait states are active.
|-
|400000-7FFFFF
|1-200
|Crash
|Serial flash: Unmapped address space. Appears to be subject to flash cache timing as discussed above
|-
|800000-CFFFFF
|257 | 1
|257 | 1
|Unmapped address space. These are reduced to 1 on Python Edition.
|-
|D00000-D3FFFF
|3
|1
|RAM
|-
|D40000-D657FF
|3
|1
|VRAM
|-
|D65800-D7FFFF
|3
|1
|Unmapped address space. Reads garbage.
|-
|D80000-DFFFFF
|3
|1
|Mirror of D00000-D7FFFF
|-
|Not mapped
|1
|1
|Port range [[:84PCE:Ports:0000|0000]] (mirrored every 0100 bytes)
|-
|E00000-E0FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:1000|1000]] (mirrored every 0100 bytes)
|-
|E10000-E1FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:2000|2000]] (mirrored every 0100 bytes)
|-
|E20000-E2FFFF
|3

9-12

6-8

5-6

4-5
|3

9-12

6-8

5-6

4-5
|Memory-mapped port range [[:84PCE:Ports:3000|3000]] (mirrored every 0200 bytes)

Extra cycles if bit 7 ''or'' 8 of the address is set, when cpu is running at 48Mhz.

Same at 24Mhz.

Same at 12Mhz.

Same at 6Mhz.
|-
|E30000-E3FFFF
|2
|1
|Memory-mapped port range [[:84PCE:Ports:4000|4000]] (mirrored every 1000 bytes)
|-
|E40000-EFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-
|F00000-F0FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:5000|5000]] (mirrored every 0100 bytes)
|-
|F10000-F1FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:6000|6000]] (mirrored every 0020 bytes)
|-
|F20000-F2FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:7000|7000]] (mirrored every 0100 bytes)
|-
|F30000-F3FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:8000|8000]] (mirrored every 0080 bytes)
|-
|F40000-F4FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:9000|9000]] (mirrored every 1000 bytes, possibly protected port range)
|-
|F50000-F5FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:A000|A000]] (mirrored every 0080 bytes)
|-
|F60000-F6FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:B000|B000]] (mirrored every 1000 bytes)
|-
|F70000-F7FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:C000|C000]] (mirrored every 0100 bytes)
|-
|F80000-F8FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:D000|D000]] (mirrored every 0080 bytes)
|-
|F90000-F9FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:E000|E000]] (mirrored every 0080 bytes)
|-
|FA0000-FAFFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:F000|F000]] (reads all zeros)
|-
|FB0000-FEFFFF
|2
|2
|Unmapped port range (reads all zeros)
|-
|FF0000-FFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-}

Category:84PCE:General Hardware Information

2020-04-18T15:58:04Z

Dr. D'nar: Update for new stuff

The TI-84 Plus CE and TI-83 Premium are two models new in 2015. The former is for the USA region (maybe all of North American?) and the latter is for France. The hardware is virtually identical between the two models. In 2019, a new revision beginning with revision M was introduced, using a cached serial flash chip and optionally featuring an [[84PCE:Ports:E000|ARM coprocessor]] for running Python programs.

Known hardware facts:
* eZ80 CPU
** Physical clock speed believed to be 48 MHz
** CPU performance is severely constrained by wait states for accessing RAM and flash
** On devices manufactured before revision M, the effective clock is speed between 8-16 MHz depending on ratio of RAM to flash accesses
** On later devices, the effective clock speed may be closer to 20 MHz, depending on RAM-to-flash access ratio as well as cache utilization
* 4 MB flash chip
** Bottom-boot organization this time
* 256 K main RAM
* Memory-mapped LCD
** 153600 bytes of VRAM confirmed, unknown if more exists
** Possibly an ARM Primecell PL111[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0293c/index.html <nowiki>[HTML]</nowiki>][http://infocenter.arm.com/help/topic/com.arm.doc.ddi0293c/DDI0293.pdf <nowiki>[PDF]</nowiki>]
* French version has testing LED; American version may get a testing LED in the future
* User programs are prohibited from using any IN/OUT instructions
** OUT causes a reset
** IN produces a constant value
* There is memory-mapped I/O, starting at E00000. Most port ranges have a mapped address, and RAM programs are allowed to use the memory-mapped I/O.
** The 00xx range of ports is not mapped. This range includes permissions control, flash control, the testing LED, NMI control, and possibly master power management.
* Flash starts at $000000
** There is also still a flash unlock sequence
* RAM starts at $D00000
* Assembly programs and TI-BASIC programs are limited to one sector (64KB)
* VRAM starts at $D40000
** VRAM is executable
* USB IP is the Faraday FOTG210

84PCE:Ports:1005

2020-04-18T15:24:16Z

Dr. D'nar: Notice of applicability

[[Category:84PCE:Ports:By_Address|1005 - Flash Wait States]] [[Category:84PCE:Ports:By_Name|Flash Wait States]]
== Synopsis ==
'''Port Number:''' 1005

'''Memory-mapped Address:''' E00005

'''Function:''' Controls flash wait states. Each read from flash will have at least 5 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 9 wait state penalty, for a total of 10 clock cycles to read a byte from flash. (V/RAM gets 3 wait states for reads, and 1 waitvstate for writes, for totals of 4 and 2, respectively.)

This port is only applicable to older devices which feature a [[84PCE:Ports:1000|parallel flash chip.]]

== Details ==
{|-
|Value   
|Effect   
|-
|00
|Instant hard crash & reset if OS ISR is enabled
|-
|01
|Makes OS a little faster, perhaps 30%. Used by the C toolchain between [https://github.com/CE-Programming/toolchain/commit/76c6620b33c550637e97a8e67ae4e6a788d7d113#diff-acbd510f12643ca0895f22a9f30a5a8cR55 October 2016] and [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047#diff-acbd510f12643ca0895f22a9f30a5a8cL55 April 2017]. Occasional crashes reported on calculators across all revisions (see: [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047 fix commit message], [https://tiplanet.org/forum/viewtopic.php?f=8&t=19535 this post]). Not recommended for regular use.
|-
|02
|Used by the C toolchain between [https://github.com/CE-Programming/toolchain/commit/9356661e7e57cd85b54b98a618d3a91891a59da7#diff-cc616a714307890453270fae8f0ff646R60 April 2016] and [https://github.com/CE-Programming/toolchain/commit/76c6620b33c550637e97a8e67ae4e6a788d7d113#diff-acbd510f12643ca0895f22a9f30a5a8cL54 October 2016]. Insufficient usage data was collected to determine the stability of this value.
|-
|03
|Used by the C toolchain since [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047#diff-acbd510f12643ca0895f22a9f30a5a8cR55 February 2017]. No crashes attributed to this value (as of April 2018).
|-
|04
|Normal value
|-
|10
|OS feels noticeably sluggish
|-
|20
|OS is unbearably sluggish
|-
|FF
|Don't even bother trying to do anything
|}

84PCE:Ports:1002

2020-04-18T15:22:50Z

Dr. D'nar: Notice of applicability

[[Category:84PCE:Ports:By_Address|1002 - Flash chip size]] [[Category:84PCE:Ports:By_Name|Flash chip size]]
== Synopsis ==
'''Port Number:''' 1002

'''Function:''' Memory-mapped flash chip size. This port is only applicable to older devices which feature a [[84PCE:Ports:1000|parallel flash chip.]]

== Details ==
=== Bits [2:0] ===
Sets the flash chip size. 06 is the default (4 MB). 07 will map 8 MB, which will cause the 4 MB to be mirrored twice. Smaller values map less flash, possibly down to 64 K.

=== Bit 3 ===
When this bit is set, the flash mapping is forced to 64KB (the equivalent of a 0 in bits 0-2).

=== Bits [7:4] ===
Writes have no apparent effect, value does not latch.

User:Zeroko

2020-04-08T20:35:51Z

Dr. D'nar: Creating user page for new user.

I am a Christian, geek girl, programmer, & somewhat of a reverse engineer.

User talk:Zeroko

2020-04-08T20:35:51Z

Dr. D'nar: Welcome!

WikiTI:Terms of Service

2020-04-08T20:22:03Z

Dr. D'nar: Create page

# Don't be a dick.

83Plus:Ports:16

2020-03-04T01:25:17Z

Dr. D'nar:

[[Category:83Plus:Ports:By_Address:Protected|16 - Flash Sector Exclusion]] [[Category:83Plus:Ports:By_Address|16 - Flash Page Exclusion]] [[Category:83Plus:Ports:By_Name|Flash Page Exclusion]]
{{Protected Port}}

== Synopsis ==
'''Port Number:''' 16h

'''Function:''' Flash Sector/Page Exclusion

This port controls which sectors or pages of Flash may contain executable code.

=== Read Values ===
* Nothing useful (mirror of [[83Plus:Ports:14|port 14]], I think.)

=== Write Values ===
* Each bit maps to a page, as determined by [[83Plus:Ports:05|port 5]]. Set a bit to disallow execution on that page.

== Comments ==
The above only applies to the 83+ basic. It does nothing on other models.

This port is protected, just as [[83Plus:Ports:14|port 14]] is; it is the only other protected port in the original hardware. Note that as with most protected ports, Flash must be write-enabled for writing to have any effect.

It is used, as are ports [[83Plus:Ports:22|22]] and [[83Plus:Ports:23|23]] on the SE, to prevent code in the archive from executing, thus theoretically limiting Flash execution privileges to FlashApps.

=== An alternate version? ===
The TI-73 uses this port differently. Instead of controlling individual pages, each bit corresponds to a Flash ''sector:''

* Bit 0: Set if execution is not allowed in sector SA2 (pages 08-0B.)
* Bit 1: Set if execution is not allowed in sector SA3 (pages 0C-0F.)
* Bit 2: Set if execution is not allowed in sector SA4 (pages 10-13.)
* Bit 3: Set if execution is not allowed in sector SA5 (pages 14-17.)

== Credits and Contributions ==
* '''Tijl Coosemans:''' Documentation [http://tijl.ulyssis.be/83phwinfo.txt here].

== See Also ==
* [[83Plus:Ports:05#Synopsis (TI-83 Plus)|Port 5]]
* [[83Plus:Ports:22|Port 22]]
* [[83Plus:Ports:23|Port 23]]

83Plus:Ports:55

2020-03-04T01:18:04Z

Dr. D'nar:

[[Category:83Plus:Ports:By Address|55 - USB Interrupt State]] [[Category:83Plus:Ports:By Name|USB Interrupt State]]
{{84P-Only Port|05}}
== Synopsis ==
'''Port Number:''' 55h

'''Function:''' USB Interrupt State

This port reports which USB interrupts have occurred.

=== Read Values ===
* Bit 0: Normally set. Cleared if the bus goes into suspend mode.
* Bit 1: Normally set. This interrupt is related to ports 4F and 50.
* Bit 2: Normally set. Cleared if a USB line interrupt (ports 56 and 57) has occurred.
* Bit 3: Normally set. BrandonW's ViewScreen experiments suggest that this gets reset if the ViewScreen-over-USB logic misses a byte, possibly because you're sending them too fast.
* Bit 4: Normally set. Cleared if a USB protocol interrupt (ports 80+) has occurred.
* Bit 5: Always 0
* Bit 6: Always 0
* Bit 7: Always 0

=== Write Values ===
* No effect

== Comments ==
Normally, the value of this port will be 1Fh. When a USB interrupt occurs, one or more of the bits will be cleared.

USB line interrupts are triggered when one of the four functional USB lines changes from low to high or high to low. [[83Plus:Ports:57|Port 57]] controls when these interrupts occur. When a line interrupt occurs, [[83Plus:Ports:56|port 56]] tells you which of the lines has changed. Use port 57 to acknowledge the interrupt.

USB protocol interrupts are triggered when (a) a USB device-level event occurs, such as a bus reset, or (b) a USB transaction finishes. [[83Plus:Ports:5B|Port 5B]] controls whether these interrupts occur. When one does, ports [[83Plus:Ports:82|82]], [[83Plus:Ports:84|84]], and [[83Plus:Ports:86|86]] (and possibly 83 and 85) will tell you what event(s) caused the interrupt. Reading from any of these ports also clears it and acknowledges the interrupt.

Bit 0 indicates some other, and uncommon, type of event - possibly that the bus has been suspended. I think that this is also controlled by port 5B, and zeroing port 5B will acknowledge the interrupt. This should be tested.