WikiTI - User contributions [en]

84PCE:Ports:000C

2022-05-21T01:14:33Z

Zeroko: Typo in port number

[[Category:84PCE:Ports:By_Address|000C - GPIO B OUT]] [[Category:84PCE:Ports:By_Name|GPIO B OUT]]
== Synopsis ==
'''Port Number:''' 000C

'''Function:''' GPIO B Output

== Details ==

These GPIOs appear to be connected to battery info.

=== Bits [0] ===
Set while USB is connected to disable the charging circuit. Reset to re-enable charging.

=== Bits [7:1] ===
TBD

84PCE:Ports:000C

2022-05-21T01:13:45Z

Zeroko: Charging circuit control

[[Category:84PCE:Ports:By_Address|000C - GPIO B OUT]] [[Category:84PCE:Ports:By_Name|GPIO B OUT]]
== Synopsis ==
'''Port Number:''' 000B

'''Function:''' GPIO B Output

== Details ==

These GPIOs appear to be connected to battery info.

=== Bits [0] ===
Set while USB is connected to disable the charging circuit. Reset to re-enable charging.

=== Bits [7:1] ===
TBD

84PCE:Ports:1000

2022-01-22T04:38:54Z

Zeroko: Added need for flash unlock on M+

[[Category:84PCE:Ports:By_Address|1000 - Flash Controller]] [[Category:84PCE:Ports:By_Name|Flash Controller]]
== Synopsis ==
'''Port Number:''' 1000-1FFF

'''Memory-mapped Address:''' E00000

'''Function:''' Flash Controller

== Parallel Controller ==

For more information see the [[83Plus:OS:Raw_Flash_Commands|parallel commands]].

{|-
|Port   
|Default   
|Bits   
|Information   
|-
|1000
|01
|01
|Reset bit 0 to crash. Seems to reduce minimum flash wait states to 2.
|-
|[[:84PCE:Ports:1001|1001]]
|00
|??
|Freeze if write value greater than 3F
|-
|[[:84PCE:Ports:1002|1002]]
|06
|0F
|Mapped flash chip address space size.
|-
|[[:84PCE:Ports:1003|1003]]
|00
|FF
|Latches value written
|-
|[[:84PCE:Ports:1003|1004]]
|00
|FF
|Latches value written
|-
|[[:84PCE:Ports:1005|1005]]
|00
|FF
|Added flash wait states over 5.
|-
|[[:84PCE:Ports:1006|1006]]
|00
|FF
|Latches value written
|-
|[[:84PCE:Ports:1007|1007]]
|FF
|FF
|Latches value written
|-
|[[:84PCE:Ports:1008|1008]]
|00
|01
|Latches value written
|-
|[[:84PCE:Ports:1009|1009]]
|00
|FF
|Ports 1009-100F latch value written
|-
|}

== Serial Controller ==

Only used in HW revisions M and later (NB: all python edition calcs are M+). Flash must be unlocked in order to write to these ports, or the write will be ignored.

For more information see the [[84PCE:OS:Serial_Flash_Commands|serial commands]].

{|-
|Port   
|Default   
|Bits   
|Information   
|-
|1005
|00
|FF
|Probably ignored for compatibility with the parallel interface.
|-
|[[:84PCE:Ports:1010|1010]]
|00
|01
|Latches value written
|-
|[[:84PCE:Ports:1011|1011]]
|00
|FF
|Ports 1011-1017 latch value written
|-
|1800
|00000000
|FFFFFFFF
|Extra data to send after command byte (usually used for a flash address).
|-
|1804
|00
|07
|How many bytes from ports $1800-$1803 to send after the command byte.
|-
|1805
|00
|00
|Unknown, something to do with the current flash command, always seems to be $00.
|-
|1806
|00
|07
|Number of dummy bytes after command byte.
|-
|1807
|00
|11
|Unknown, something to do with the current flash command. Bit 0 is always set and bit 4 is rarely set.
|-
|1808
|00000000
|FFFFFFFF
|Number of bytes to transfer through port $1900 with the current flash command.
|-
|180C
|00
|C6
|Bit 1 might be direction (0 = in, 1 = out). Other bits unknown.
|-
|180D
|0000
|B000
|Unknown, something to do with the current flash command, usually $0000, rarely $B000.
|-
|180F
|00
|FF
|Current command byte.
|-
|1818
|00
|03
|Bit 0/1 is set when bytes can be written/read through port $1900.
|-
|1824
|00
|01
|Bit 0 set when the command finishes and the busy bit is cleared, write 1 to clear.
|-
|182C-182F
|FFC00000
|FFFFFFFF
|Address mask for memory-mapped access to flash.
|-
|1830
|00000000
|FFFFFFFF
|Unknown.
|-
|1900
|00
|FF
|Read or write command data.
|-
|}

Category:84PCE:General Hardware Information

2021-12-09T19:35:00Z

Zeroko: Changed reset length threshold

The TI-84 Plus CE and TI-83 Premium are two models new in 2015. The former is for the USA region (maybe all of North American?) and the latter is for France. The hardware is virtually identical between the two models. In 2019, a new revision beginning with revision M was introduced, using a cached serial flash chip and optionally featuring an [[84PCE:Ports:E000|ARM coprocessor]] for running Python programs.

Known hardware facts:
* eZ80 CPU
** Physical clock speed believed to be 48 MHz
** CPU performance is severely constrained by wait states for accessing RAM and flash
** On devices manufactured before revision M, the effective clock is speed between 8-16 MHz depending on ratio of RAM to flash accesses
** On later devices, the effective clock speed may be closer to 20 MHz, depending on RAM-to-flash access ratio as well as cache utilization
* 4 MB flash chip
** Bottom-boot organization this time
* 256 K main RAM
* Memory-mapped LCD
** 153600 bytes of "VRAM" (actually just RAM) confirmed
** Possibly an ARM Primecell PL111[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0293c/index.html <nowiki>[HTML]</nowiki>][http://infocenter.arm.com/help/topic/com.arm.doc.ddi0293c/DDI0293.pdf <nowiki>[PDF]</nowiki>]
* French version (TI-83 Premium CE), and other european versions (TI-84 Plus CE-T), have an LED on top for exams
* User programs are prohibited from using any IN/OUT instructions
** OUT causes a reset
** IN produces a constant value
* There is memory-mapped I/O, starting at E00000. Most port ranges have a mapped address, and RAM programs are allowed to use the memory-mapped I/O.
** The 00xx range of ports is not mapped. This range includes permissions control, flash control, the testing LED, NMI control, and possibly master power management.
* Flash starts at $000000
** There is also still a flash unlock sequence
* RAM starts at $D00000
* Assembly programs and TI-BASIC programs are limited to one sector (64KB)
* VRAM starts at $D40000
** VRAM is executable
* USB IP is the Faraday FOTG210
* The reset button on the back resets the CPU, but may not always reset RAM
** Briefly pressing reset (for shorter than about 1.5 seconds) results in the calculator turning on if it was off. On revisions before M, the boot code always clears RAM, while on revision M or later, the boot code does not clear RAM, but the OS might under some circumstances. This is the same behavior as RST 00.
** Holding reset for longer than about 1.5 seconds results in the calculator turning off if it was on; regardless of revision, RAM is cleared.
** If charging via USB, a long press behaves exactly like a short press.

Category:84PCE:General Hardware Information

2021-12-09T07:35:59Z

Zeroko: Reset button behavior

The TI-84 Plus CE and TI-83 Premium are two models new in 2015. The former is for the USA region (maybe all of North American?) and the latter is for France. The hardware is virtually identical between the two models. In 2019, a new revision beginning with revision M was introduced, using a cached serial flash chip and optionally featuring an [[84PCE:Ports:E000|ARM coprocessor]] for running Python programs.

Known hardware facts:
* eZ80 CPU
** Physical clock speed believed to be 48 MHz
** CPU performance is severely constrained by wait states for accessing RAM and flash
** On devices manufactured before revision M, the effective clock is speed between 8-16 MHz depending on ratio of RAM to flash accesses
** On later devices, the effective clock speed may be closer to 20 MHz, depending on RAM-to-flash access ratio as well as cache utilization
* 4 MB flash chip
** Bottom-boot organization this time
* 256 K main RAM
* Memory-mapped LCD
** 153600 bytes of "VRAM" (actually just RAM) confirmed
** Possibly an ARM Primecell PL111[http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0293c/index.html <nowiki>[HTML]</nowiki>][http://infocenter.arm.com/help/topic/com.arm.doc.ddi0293c/DDI0293.pdf <nowiki>[PDF]</nowiki>]
* French version (TI-83 Premium CE), and other european versions (TI-84 Plus CE-T), have an LED on top for exams
* User programs are prohibited from using any IN/OUT instructions
** OUT causes a reset
** IN produces a constant value
* There is memory-mapped I/O, starting at E00000. Most port ranges have a mapped address, and RAM programs are allowed to use the memory-mapped I/O.
** The 00xx range of ports is not mapped. This range includes permissions control, flash control, the testing LED, NMI control, and possibly master power management.
* Flash starts at $000000
** There is also still a flash unlock sequence
* RAM starts at $D00000
* Assembly programs and TI-BASIC programs are limited to one sector (64KB)
* VRAM starts at $D40000
** VRAM is executable
* USB IP is the Faraday FOTG210
* The reset button on the back resets the CPU, but may not always reset RAM
** Briefly pressing reset results in the calculator turning on if it was off. On revisions before M, the boot code always clears RAM, while on revision M or later, the boot code does not clear RAM, but the OS might under some circumstances. This is the same behavior as RST 00.
** Holding reset for longer (5 seconds works) results in the calculator turning off if it was on; regardless of revision, RAM is cleared.
** If charging via USB, a long press behaves exactly like a short press.

86:LCD Controller

2021-09-22T12:59:03Z

Zeroko: Added link to ASIC & replaced port 4 with 04 to match usage elsewhere.

[[Category:86:General Hardware Information|LCD Controller]]
The TI-86 has a memory-mapped STN liquid crystal display. The main portion of LCD controller is inside the [[86:ASIC|ASIC]], with row & column drivers & circuitry to produce the necessary voltages located on a daughterboard on which the LCD itself is also mounted.

== DMA ==
When the LCD is enabled, the ASIC needs to send pixels to it continuously. In order to allow the CPU to operate at the same time, the ASIC contains an internal buffer used to hold the pixels for the current row. This buffer is filled via DMA (direct memory access) that pauses the CPU once per row. This pause appears to be implemented internally by way of the Z80 signals /BUSREQ & /BUSACK, & as such, it is even able to occur in between the M cycles of a single instruction. No DMA is performed when the LCD is disabled.

The LCD always uses all 64 rows per physical frame. If the number of rows per logical frame is set lower than 64 via bits 1-2 of [[86:Ports:04|Port 04]], the subsequent logical frames are stacked vertically until the whole 64 rows are filled, with the last one being cut short if the rows per frame is set to 48. This stacking also makes the image darker, presumably because it increases the effective duty cycle.

The LCD controller always sends 160 pixels per row to the daughterboard, of which the first 80 & last 48 are visible on screen, for a total of 128 visible columns. However, DMA only reads as many bytes as necessary to contain the number of columns chosen via bits 3-4 of [[86:Ports:04|Port 04]]. Of the columns read via DMA, the first 80 are placed at the beginning of the buffer, & the remainder are placed at the end of the buffer. If this is fewer than the full 160 columns, the 4 columns immediately after the first 80 are copied from the last 4 of the previous row's DMA transfer. The remaining columns are copied starting from the beginning of the current row's DMA transfer.

== Interrupts ==
LCD interrupts occur twice per logical frame. They occur one row after one quarter & three quarters of the way down the frame, which is rows 17 & 49 (counting from 0) when set to 64 rows per frame. DMA occurs after the interrupt acknowledgement, which in particular is after the CPU reads the byte used to determine which offset to use for IM 2. The start of the interrupt service routine itself is then delayed until DMA finishes.

Warning: Toggling individual pixels every other interrupt may damage the LCD by causing a net charge to accumulate. Any given pixel's value should only be changed (at most) once every fourth interrupt. This is because the pixels of STN LCDs must be driven using AC waveforms to prevent damage due to charge buildup, & the calculator achieves this by alternating between 2 sets of voltages on consecutive frames.

86:ASIC

2021-09-22T12:56:24Z

Zeroko: Created page with "The ASIC used in all known revisions of the TI-86 is an 80-pin QFP with part number T6A43. It contains a Z80-compatible CPU core & additional logic that implements the :Cate..."

The ASIC used in all known revisions of the TI-86 is an 80-pin QFP with part number T6A43. It contains a Z80-compatible CPU core & additional logic that implements the [[:Category:86:Ports:By_Address|I/O ports]], as well as the [[86:LCD_Controller|LCD Controller]]. It is also used in some TI-81 revisions, the TI-85, & the PS-6600 Organizer.

== CPU ==
The CPU is a CMOS Z80 clocked around 5-6 MHz depending on the battery level. An extra wait state is automatically inserted during every M1 cycle, so instruction timings need to be adjusted accordingly for timing-critical code. The LCD controller pauses the CPU during DMA using internal /BUSREQ & /BUSACK signals (or some behaviorally-equivalent mechanism), which will not interrupt an M cycle but can occur between M cycles of a single instruction. As a result, behavior that depends on bus content (such as reading from [[86:Memory_Mapping#Unused_Banks|Unused Banks]]) can be altered by DMA happening in the middle of an instruction. DMA also affects timing-critical code, & can only be disabled by turning the LCD off entirely (via bit 3 of [[86:Ports:03|Port 03]]).

== Pinout ==
The pins are numbered counterclockwise around the ASIC package when viewed from above. Pins 1, 25, 41, & 65 are labeled on the PCB, although the label for 25 is offset from the actual pin due to other components being in the way. These labels are taken from [https://www.ticalc.org/archives/files/fileinfo/32/3240.html this schematic for the TI-85], since it uses the same ASIC, except where those labels are incorrect. Pins with labels prefixed by a slash (/) are active low. The additional signal names for V1-V15 are taken from the datasheets for the T6A23 column driver & T6A40 row driver on the LCD daughterboard.

{|
|-
! colspan="3" | Right side from bottom to top
|-
| 1. || A2 || A0-A19 are the address bus.
|-
| 2. || A1
|-
| 3. || A0
|-
| 4. || D7 || D0-D7 are the data bus.
|-
| 5. || D6
|-
| 6. || D5
|-
| 7. || D4
|-
| 8. || D3
|-
| 9. || D2
|-
| 10. || D1
|-
| 11. || D0
|-
| 12. || LCDOSCGND || LCD oscillator ground. (Usage of pins 12-14 for the LCD controller clock needs verification.)
|-
| 13. || LCDOSC1
|-
| 14. || LCDOSC2
|-
| 15. || /ON
|-
| 16. || KR0 || KR0-KR7 are keypad rows 0-7, corresponding to the bits of [[86:Ports:01|Port 01]] when written.
|-
| 17. || KR1
|-
| 18. || KR2
|-
| 19. || KR3
|-
| 20. || KR4
|-
| 21. || KR5
|-
| 22. || KR6
|-
| 23. || KR7
|-
| 24. || KC0 || KC0-KC7 are keypad columns 0-7, corresponding to the bits of Port 01 when read.
|-
! colspan="3" | Top side from right to left
|-
| 25. || KC1
|-
| 26. || KC2
|-
| 27. || KC3
|-
| 28. || KC4
|-
| 29. || KC5
|-
| 30. || KC6
|-
| 31. || KC7
|-
| 32. || VCC
|-
| 33. || V15 || Bit 0 of [[86:Ports:02|Port 02]] (contrast); V1-V15 are connected to the LCD daughterboard.
|-
| 34. || V14 || Bit 1 of Port 02
|-
| 35. || V13 || Bit 2 of Port 02
|-
| 36. || V12 || Bit 3 of Port 02
|-
| 37. || V11 || Bit 4 of Port 02
|-
| 38. || V10 || (Unknown; apparently contrast-related)
|-
| 39. || V9 || (Unknown; apparently contrast-related)
|-
| 40. || V8 || FR (frame): alternates on consecutive frames to ensure LCD drive voltages alternate.
|-
! colspan="3" | Left side from top to bottom
|-
| 41. || V7 || FP (frame pulse) & DIO1: starts a frame.
|-
| 42. || V6 || LP (latch pulse) & EIO1: starts a row.
|-
| 43. || V5 || SCP (shift clock pulse): pixel clock.
|-
| 44. || V4 || DI4; DI1-DI4 are pixel data.
|-
| 45. || V3 || DI3
|-
| 46. || V2 || DI2
|-
| 47. || V1 || DI1
|-
| 48. || IORQ || External I/O enable; used for [[86:Ports:20|Ports 20-3F]] (active high, unlike the Z80 signal). Apparently also used by prototype TI-86es with flash ROM as the flash chip's output enable signal (needs clarification).
|-
| 49. || CPUOSCGND || CPU oscillator ground.
|-
| 50. || CPUOSC1
|-
| 51. || CPUOSC2
|-
| 52. || GND
|-
| 53. || /INT || External interrupt request (needs verification); see bit 2 of [[86:Ports:03|Port 03]].
|-
| 54. || LP0 || LP0-LP3 are the corresponding bits of [[86:Ports:07|Port 07]]
|-
| 55. || LP1
|-
| 56. || LP2
|-
| 57. || LP3
|-
| 58. || /CE0 || /CE0-/CE3 are chip enables for memory banks (see [[86:Memory_Mapping|Memory Mapping]])
|-
| 59. || /CE1
|-
| 60. || /CE2
|-
| 61. || /CE3
|-
| 62. || /WE || Write enable. Note that there is no output enable.
|-
| 63. || A19
|-
| 64. || A18
|-
! colspan="3" | Bottom from left to right
|-
| 65. || A17
|-
| 66. || A16
|-
| 67. || A15
|-
| 68. || A14
|-
| 69. || A13
|-
| 70. || A12
|-
| 71. || VCC
|-
| 72. || A11
|-
| 73. || A10
|-
| 74. || A9
|-
| 75. || A8
|-
| 76. || A7
|-
| 77. || A6
|-
| 78. || A5
|-
| 79. || A4
|-
| 80. || A3
|}

86:Interrupts

2021-09-21T07:01:28Z

Zeroko: Added brief description of OS ISR & its user interrupt handler support

[[Category:86:General Hardware Information|Interrupts]]

Individual interrupt sources can be enabled, disabled, or acknowledged using [[86:Ports:03|Port 3]]. When an interrupt occurs, the CPU automatically masks interrupts, so there is no need to start with DI. Interrupts must be acknowledged before executing EI, or the interrupt will retrigger immediately after the instruction following the EI is executed. RET & RETI have the same effects on the TI-86, so RET can be used to save one byte.

There is no way to cause a non-maskable interrupt, so the OS does not have an NMI handler.

== Interrupt Mode 0 ==
When an interrupt occurs, the CPU treats the current bus content as an opcode & executes it. If the interrupt source was the [[86:LCD_Controller|LCD Controller]], this will be the last byte transferred by DMA. For any other interrupt source, it will be the last byte accessed by the instruction that was executing when the interrupt condition arose, either as part of the instruction itself or as a memory operand. If the resulting opcode requires additional opcode or operand bytes, they will all have the same value fetched from the address in PC without changing the value of PC. Under normal circumstances, IM 0 is likely to result in a crash.

== Interrupt Mode 1 ==
When an interrupt occurs, the CPU pushes the return address & then jumps to address 0038h. Note that ROM access should not be disabled (see bit 6 of [[86:Ports:04|Port 4]]) while IM 1 is set & interrupts are enabled, or the calculator will likely crash.

The first thing the OS interrupt service routine does (after doing EX AF,AF' & EXX to preserve the registers of the code that was interrupted) is to check whether bit 2 of (IY+23h) is set. If so, it will call the user interrupt handler, provided its checksum is correct. The user interrupt handler starts execution at address D2FEh, & the last usable byte is at D2C5h. The checksum, which is stored at D2FDh, must contain the sum of the bytes stored at D2FEh, D325h, D34Dh, D375h, D39Dh, & D3C5h, or else the aforementioned IY flag will be cleared instead of executing the handler.

If the user handler is not set (or after it returns), the OS checks if ON triggered the interrupt. If so, it either turns the calculator on (if it was off), turns the calculator off (if 2nd was pressed), or makes note of ON having been pressed. Regardless of the interrupt type, it then checks the keypad state, updates the cursor & run indicator if they are enabled, & updates the APD timer. If the APD timer expires, it turns the calculator off after setting a flag (bit 4 of (IY+08)) to indicate that it should resume where it left off instead of returning to the home screen. (Note that certain special cases have been ignored in this description.)

== Interrupt Mode 2 ==
When an interrupt occurs, the CPU treats the current bus content as the lower 8 bits of an address, with the upper 8 bits being the value of the I register. Regardless of interrupt source, the bus content will be the last byte accessed (either as part of the opcode or as a memory operand) by the instruction that was executing when the interrupt condition arose, because if [[86:LCD_Controller#DMA|LCD DMA]] occurs, it takes place after the CPU reads the previous bus content. The CPU then pushes the return address & jumps to the address stored at the address saved earlier. If the first or both of the bytes of this new address are read from an [[86:Memory_Mapping#Unused_Banks|unused bank]], their value will be the lower 8 bits of the return address. If just the second byte is read from an unused bank, its value will be the same as the first.

86:Interrupts

2021-09-21T04:38:19Z

Zeroko: Fixed behavior of IM 2 vectors in unused banks

86:Interrupts

2021-09-21T04:34:04Z

Zeroko: Created page with "Interrupts Individual interrupt sources can be enabled, disabled, or acknowledged using Port 3. When an interrupt..."

84PCE:Wait States

2021-09-20T20:32:38Z

Zeroko: Updated unmapped address space known revision range

[[Category:84PCE:General_Hardware_Information|Wait States]]
== Synopsis ==
The eZ80 processor is able to perform a memory access in a single cycle. However, on the TI-84+CE, accesses will actually take longer due to wait states. For example, a read from RAM will take 4 cycles, because it has 3 wait states. The wait states for parallel Flash accesses can be customized, but it is unknown whether that is the case for other memory regions or for the newer serial flash.

== Flash Access Wait States ==

=== Parallel Flash ===
Calculators produced prior to revision M use a parallel flash chip. These chips are limited to a maximum read rate under 20 MHz, necessitating at least 1 wait state for the ASIC's faster 48 MHz clock. The ASIC's internal memory mapping hardware adds a minimum of 5 wait states just to ferry the request to the flash chip and the response back to the CPU, but additional external wait states are required for the flash chip to make its reply. See [[84PCE:Ports:1005]] for more information.

=== Serial Flash ===
Calculators produced starting in 2019 with revision M no longer use a parallel flash chip, but instead an SPI flash chip. This flash chip needs much longer to initially retrieve data from a random address, but can stream sequential data at a reasonable rate. A new ASIC design takes advantage of this capability by adding a cache between the flash chip and CPU.

According to tests performed by [[User:Jacobly|Jacobly]], the cache is 8 K in size, structured as a 2-way set associative cache with 128 sets of 32 bytes chosen by address bits 5-11. A fetch from the same cache line as previously accessed costs 1 wait state (so the read takes a total of 2 cycles), a fetch from a different cache line costs 2 wait states, and a cache miss costs 194-200 wait states.

Code execution from flash displays high locality of reference, so amortized performance should be reasonably good, although the 200 cycle penalty for a cache miss probably hurts a fair bit. For flash-resident data files, programmers should try to organize them to keep related data together to maximize cache utilization. A good access pattern can make accessing data in flash twice as fast as getting it from RAM, while a bad pattern can make it substantially worse than even pulling it from the old parallel flash.

== LCD DMA ==
The LCD controller uses Direct Memory Access to retrieve the pixels from RAM. However, since the CPU and the LCD controller cannot access RAM at the same time, there are some waitstates caused asynchronously by the DMA during RAM accesses. The rate of waitstates caused by the DMA appears to be directly proportional to the rate of data being sent to the screen, so lower bit-per-pixel modes will reduce the general performance hit.

== Wait State Layout ==
{|-
|Address Range   
|Read   
|Write   
|Description   
|-
|000000-3FFFFF
|5+
|Crash
|[[84PCE:Ports:1000|Parallel flash]]: Wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. The OS sets a total of 9 wait states.
|-
|000000-3FFFFF
|1-200
|Crash
|[[84PCE:OS:Serial_Flash_Commands|Serial flash:]] See above discussion.
|-
|400000-7FFFFF
|257
|Crash
|Parallel flash: Unmapped address space. Can be mapped to Flash using [[:84PCE:Ports:1002|1002]], after which Flash wait states are active.
|-
|400000-BFFFFF
|1-200
|Crash
|Serial flash: Flash mirrors. Appears to be subject to flash cache timing as discussed above
|-
|800000-CFFFFF
|257
|257
|Parallel flash: Unmapped address space.
|-
|C00000-CFFFFF
|1
|1
|Serial flash: Unmapped address space.
|-
|D00000-D3FFFF
|3
|1
|RAM
|-
|D40000-D657FF
|3
|1
|VRAM
|-
|D65800-D72BFF
|3
|1
|Unmapped address space. Reads garbage.
|-
|D72C00-D7FFFF
|3
|1
|Unmapped address space. Reads garbage (revisions up to at least C) or mirror of D52C00-D5FFFF (at least I-S).
|-
|D80000-DFFFFF
|3
|1
|Mirror of D00000-D7FFFF
|-
|Not mapped
|1
|1
|Port range [[:84PCE:Ports:0000|0000]] (mirrored every 0100 bytes)
|-
|E00000-E0FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:1000|1000]] (mirrored every 0100 bytes)
|-
|E10000-E1FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:2000|2000]] (mirrored every 0100 bytes)
|-
|E20000-E2FFFF
|3

9-12

6-8

5-6

4-5
|3

9-12

6-8

5-6

4-5
|Memory-mapped port range [[:84PCE:Ports:3000|3000]] (mirrored every 0200 bytes)

Extra cycles if bit 7 ''or'' 8 of the address is set, when cpu is running at 48 MHz.

Same at 24 MHz.

Same at 12 MHz.

Same at 6 MHz.
|-
|E30000-E3FFFF
|2

2

2

2

2

3

1

1

1

1
|1

20-21/22

15/13

11

9

3

15-16/13

12/10

10/8

8
|Memory-mapped port range [[:84PCE:Ports:4000|4000]] (mirrored every 1000 bytes)

Special timing for 4000-400F & 4018-401B (pre-M/M+) at 48 MHz

Same at 24 MHz

Same at 12 MHz

Same at 6 MHz

Special timing for 4200-43FF (any CPU speed)

Special timing for 4C00-4DFF (pre-M/M+) at 48 MHz

Same at 24 MHz

Same at 12 MHz

Same at 6 MHz
|-
|E40000-EFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-
|F00000-F0FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:5000|5000]] (mirrored every 0100 bytes)
|-
|F10000-F1FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:6000|6000]] (mirrored every 0020 bytes)
|-
|F20000-F2FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:7000|7000]] (mirrored every 0100 bytes)
|-
|F30000-F3FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:8000|8000]] (mirrored every 0080 bytes)
|-
|F40000-F4FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:9000|9000]] (mirrored every 1000 bytes, possibly protected port range)
|-
|F50000-F5FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:A000|A000]] (mirrored every 0080 bytes)
|-
|F60000-F6FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:B000|B000]] (mirrored every 1000 bytes)
|-
|F70000-F7FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:C000|C000]] (mirrored every 0100 bytes)
|-
|F80000-F8FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:D000|D000]] (mirrored every 0080 bytes)
|-
|F90000-F9FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:E000|E000]] (mirrored every 0080 bytes)
|-
|FA0000-FAFFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:F000|F000]] (mirrored every 0100 bytes)
|-
|FB0000-FEFFFF
|2
|2
|Unmapped port range (reads all zeros)
|-
|FF0000-FFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-}

Category:84PCE:RAM:By Address

2021-09-20T20:32:30Z

Zeroko: Updated unmapped address space known revision range

See also [[:Category:84PCE:RAM:By Name|list of RAM areas by name]].

Please read our page on [[Contributing]] before editing these pages!

The eZ80 has a 24-bit linear address space. Layout:
* 000000h: Start of flash. The first 128 K are locked boot sectors. The first 8 are divided into 8 K sectors, all of which are locked. The certificate is now a single 64 K sector, so I hope you don't crash while rebuilding it.
* 000066h: Flash exception handler. Write-to-flash without permission triggers the non-maskable interrupt to fire.
* 00007Eh: Hardware/Emu flag: This byte indicates whether the ROM is a hardware ROM or emulator.
* 000080h: Start of boot code jump table.
* 020000h: Start of OS.
* 0C0000h: Start of user archive.
* 3B0000h: Certificate.
* 3C0000h: Temp RAM backup, on newer versions of TIOS debug output is also written here.
* 3E0000h: Temp RAM backup.
* 3F0000h: Temp RAM backup, temp certificate backup, swap sector.
* 400000h: Can be setup to mirror flash, but usually unmapped.
* 800000h: Always unmapped.
* D00000h: Start of RAM. 256 K.
* D1A87Eh: Top of the SPL stack.
* D1A881h: Start of UserMem.
* D40000h: Start of VRAM. 320x240x2 bytes = 153600 bytes.
* D65800h: Unmapped memory.
* D72C00h: Unmapped memory (revisions up to at least C) or mirror of D52C00h (at least I-S).
* D80000h: Mirror of D00000h.
* E00000h: Start of [[84PCE:Wait_States|memory-mapped I/O]] address spaces.

SafeRAM Areas:
* D031F6h: [[84PCE:RAM:D031F6|pixelShadow]] - 8400 bytes
* D052C6h: [[84PCE:RAM:D052C6|pixelShadow2]] - 8400 bytes
* D07396h: [[84PCE:RAM:D07396|cmdPixelShadow]] - 8400 bytes
* D09466h: [[84PCE:RAM:D09466|plotSScreen]] - 21945 bytes
* D0EA1Fh: [[84PCE:RAM:D0EA1F|saveSScreen]] - 21945 bytes
** Note that the above is contiguous, which provides a total linear free space of 69090 bytes of RAM.
** [[84PCE:RAM:D052C6|pixelShadow2]] is the most stable; and is a viable option for ''testing'' TSRs and hooks.

More SafeRAM Areas:
* D006C0h: [[84PCE:RAM:D006C0|textShadow]] - 260 bytes
* D0232Dh: [[84PCE:RAM:D0232D|cmdShadow]] - 260 bytes

Also, if you do not wish to use the LCD cursor (This is not RAM, but can be used as scrap)
* E30800h: cursorImage - 1024 bytes
[[Category:84PCE:RAM|RAM Areas by Address]]

86:Ports:20

2021-09-20T19:59:42Z

Zeroko: Created page with "20 - External I/O External I/O == Synopsis == '''Port Number:''' 20-3Fh '''Function:''' None This port range i..."

[[Category:86:Ports:By_Address|20 - External I/O]] [[Category:86:Ports:By_Name|External I/O]]
== Synopsis ==
'''Port Number:''' 20-3Fh

'''Function:''' None

This port range is meant for communication with external I/O devices, but the TI-86 has no such devices.

=== Read Values ===
Because these ports are not connected to anything, their read behavior is the same as [[86:Memory_Mapping#Unused_Banks|Unused Banks]].

=== Write Values ===
Because these ports are not connected to anything, their write behavior is the same as unused banks. That is, writes are ignored.

Category:86:Ports:By Address

2021-09-20T19:50:34Z

Zeroko: Port mirroring

[[Category:86:Ports|Ports by Address/Number]]

See also [[:Category:86:Ports:By Name|list of ports by name]].

Ports are mirrored: Adding 8, 10h, or 18h to ports in the 0-7 range will access the same port, & adding 40h, 80h, or C0h to any port will access the same port.

Please read our page on [[Contributing]] before editing these pages!

86:Ports:01

2021-09-20T19:47:19Z

Zeroko: Based on 83Plus:Ports:01, changed key labels & added battery level

[[Category:86:Ports:By_Address|01 - Keyboard]] [[Category:86:Ports:By_Name|Keyboard]]
== Synopsis ==
'''Port Number:''' 01h

'''Function:''' Keyboard Port

This port reads key presses from the keypad. The keypad is divided into a series of groups.

See also [[83Plus:Ports:01|TI-83 Plus Port 01]], which is identical apart from the key labels & the lack of battery level detection.

=== Read Values ===
* Bits are set according whether corresponding keys from selected groups are pressed. Groups are selected through writing to the port. A pressed key reads a 0 bit. An unpressed key reads a 1 bit.
* Bit 0 will also read as 0 if groups 0-2 are all selected & the battery level is low.

=== Write Values ===
* FFh : Reset the keypad. This unselects all groups and resets the keypad state.
* F8h : Check battery level. This also selects keypad groups 0-2 for monitoring.
* Anything else : Any 0 bit adds the corresponding group to the list of monitored groups. When a key in a monitored group is pressed, the corresponding key bit reads 0, otherwise it reads 1 (active-low).

== Key Map ==
The key map is laid out as follows:

{|
|
! Group Bit
| 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7
|-
|
! Group Mask
| FE || FD || FB || F7 || EF || DF || BF || 7F
|-
! Key Bit !! (Mask)
|-
! 0 !! (FE)
| DOWN||ENTER|| (-) || . || 0 || || F5 || ||
|-
! 1 !! (FD)
| LEFT|| + || 3 || 2 || 1 || STO || F4 || ||
|-
! 2 !! (FB)
|RIGHT|| - || 6 || 5 || 4 || , || F3 || ||
|-
! 3 !! (F7)
| UP || * || 9 || 8 || 7 || x2 || F2 || ||
|-
! 4 !! (EF)
| || / || ) || ( || EE || LN || F1 || ||
|-
! 5 !! (DF)
| || ^ || TAN || COS || SIN || LOG || 2nd || ||
|-
! 6 !! (BF)
| ||CLEAR||CUSTOM||PRGM ||TABLE||GRAPH||EXIT || ||
|-
! 7 !! (7F)
| || || || DEL ||x-VAR||ALPHA||MORE || ||
|}

* '''Note:''' Group FB Key FE is NEGATE, not to be confused with SUBTRACT.
* '''Note:''' Group DF Key FE would be ON, but the ON key is tested through [[86:Ports:03|Port 03]], bit 3.

== Comments ==
* The OS delays about 1400 cycles (100 iterations of a tight DJNZ loop) when checking the battery level at startup, which is much longer than used to test if keys are pressed.
* Bit 0 will be 0 when testing the battery level if the warning message would appear. However, because it is still also wired to the keypad, holding any of DOWN, ENTER, or (-) when turning the calculator on will also cause the warning message to appear.

86:Ports:03

2021-09-20T13:03:03Z

Zeroko: Fixed bit 1 & 3 write descriptions & linked to LCD controller page

[[Category:86:Ports:By_Address|03 - Interrupt Control]] [[Category:86:Ports:By_Name|Interrupt Control]]
== Synopsis ==
'''Port Number:''' 03h

'''Function:''' Interrupt Control Port

This port controls all devices that can generate interrupts.

=== Read Values ===
* Bit 0: Set if the ON key generated an interrupt.
* Bit 1: Set if the [[86:LCD_Controller|LCD controller]] generated an interrupt (after [[86:LCD_Controller#DMA|DMA]] for rows 17 & 49). Used by the OS as a periodic interrupt source (approximately 200 Hz).
* Bit 2: Set if the /INT pin generated an interrupt (unused on the TI-86).
* Bit 3: Reset if the ON key is being pressed; set otherwise.
* Bit 4-7: Unused.

=== Write Values ===
* Bit 0: Set 0 to disable ON key interrupts and to acknowledge an ON key interrupt. Set 1 to enable ON key interrupts.
* Bit 1: Set 0 to disable [[86:LCD_Controller#Interrupts|LCD controller interrupts]] & to acknowledge an interrupt from the LCD controller. Set 1 to enable interrupts from the LCD controller.
* Bit 2: Set 0 to disable external interrupts & to acknowledge an external interrupt. Set 1 to enable external interrupts.
* Bit 3: Set 0 to turn off the LCD. Set 1 to turn on the LCD. When the LCD is off, DMA & LCD interrupts do not occur.
* Bit 4-7: Unused.

== Comments ==
* You need to acknowledge interrupts. Otherwise a new interrupt will be generated directly after you enable interrupts again with EI. Because that disables that particular interrupt at the same time, you may have to write a second value to this port to re-enable it.
* The OS shuts down by turning off the LCD & HALTing with the ON key interrupt enabled.

Category:86:General Hardware Information

2021-09-20T12:56:14Z

Zeroko: No TI-86 "family"

This is the central location for generic documentation on the TI-86 hardware.

Please read our page on [[Contributing]] before editing these pages!

Category:86:General Hardware Information

2021-09-20T12:55:21Z

Zeroko: Created page with "This is the central location for generic documentation on the TI-86 family hardware. Please read our page on Contributing before editing these pages!"

This is the central location for generic documentation on the TI-86 family hardware.

Please read our page on [[Contributing]] before editing these pages!

Calculator Documentation

2021-09-20T12:52:54Z

Zeroko: Added general hardware information

== TI-83 (Regular) ==

Available Information:

* [[:Category:83:ROMCalls:By_Name|ROMCalls (System Entrypoints)]]
* [[:Category:83:Flags:By_Name|Flags]]
* [[:Category:83:OS_Information|General OS Documentation]]
* [[:Category:83:Ports:By_Address|Ports]]
* [[:Category:83:RAM:By_Name|RAM Areas]]

== TI-83 Plus Family ==

Available Information:

* [[:Category:83Plus:BCALLs:By_Name|B_CALLs (System Entrypoints)]]
* [[:Category:83Plus:Flags:By_Name|Flags]]
* [[:Category:83Plus:OS_Information|General OS Documentation]]
* [[:Category:83Plus:General_Hardware_Information|General Hardware Documentation]]
* [[:Category:83Plus:Hooks:By_Name|Hooks]]
* [[:Category:83Plus:Ports:By_Address|Ports]]
* [[:Category:83Plus:RAM:By_Name|RAM Areas]]
* [[:Category:83Plus:Basic|TI-83+ Basic]]
* [[:Category:83Plus:Quirks|Quirks]]

== TI-84+CSE ==

Available Information:

* [[:Category:84PCSE:BCALLs:By_Name|B_CALLs (System Entrypoints)]]
* [[:Category:84PCSE:Flags:By_Name|Flags]]
* [[:Category:84PCSE:OS_Information|General OS Documentation]]
* [[:Category:84PCSE:General_Hardware_Information|General Hardware Documentation]]
* [[:Category:84PCSE:Hooks:By_Name|Hooks]]
* [[:Category:84PCSE:RAM:By_Name|RAM Areas]]
* [[:Category:84PCSE:Basic|TI-83+ Basic]]
Note: Because the TI-84+CSE is based on the older TI-84+ ASIC, much of the hardware related documentation is the same. Therefore, the port list for the TI-84+CSE shall be combined with the TI-83+ ports.

== TI-84 Plus CE[-T], TI-83 Premium CE ==

Available information:

* [[:Category:84PCE:Syscalls:By_Name|System Entrypoints]]
* [[:Category:83PCE:Hooks:By_Name|Hooks]]
* [[:Category:84PCE:General_Hardware_Information|General Hardware Documentation]]
* [[:Category:84PCE:OS_Information|General OS Documentation]]
* [[:Category:84PCE:RAM:By_Address|RAM areas]]
* [[:Category:84PCE:Ports:By_Name|Ports]]

The TI-84 Plus CE and TI-83 Premium CE are two models new in 2015. The former is for the USA region (maybe all of North America?) and the latter is for France (Features a PTT LED and an exact math engine, whose new vartypes are documented [https://docs.google.com/document/d/1P_OUbnZMZFg8zuOPJHAx34EnwxcQZ8HER9hPeOQ_dtI here]). 
The hardware is virtually identical between the two models. The TI-84 Plus CE-T is the European counterpart of the TI-84 Plus CE, but has the PTT LED like the 83PCE.

== TI-86 ==

Available Information:

* [[:Category:86:ROMCalls:By_Name|ROMCalls (System Entrypoints)]]
* [[:Category:86:Flags:By_Name|Flags]]
* [[:Category:86:General_Hardware_Information|General Hardware Documentation]]
* [[:Category:86:OS_Information|General OS Documentation]]
* [[:Category:86:Ports:By_Address|Ports]]
* [[:Category:86:RAM:By_Name|RAM Areas]]

== M68K Family ==

Available Information:

* [[:Category:68k:Ports:By_Address|Ports]]

== Z80 programming ==
* [[Meta-tutorial]]
* [[:Category:Z80_Routines|Z80 Routines]]
* [[Z80 Instruction Set]]
* [[Z80 Good Programming Practices]]
* [[Z80 Optimization]]
* [[Programming cross z80 calculators]]
* [[Programming APPS vs. Ram Programs]]
* [[Programming under Unix-like operating systems]]
* [[Programming an OS for z80 calculators]]

== Calculator Software ==
* [[Notable programs]]
* [[:Category:83Plus:Software|83Plus Software Documentation]]
* [[Experiments]]

== Computer Software ==
* [[Link software]]
* [[:Category:Emulators|Emulators]]
* [[Assemblers]]
* [[Compilers]]
* [[IDEs]]
* [[Disassemblers]]

== TI Community ==

* [[Beginners|Beginners' manual]]
* [[Calculator General FAQ]]
* [[History of the TI Z80 community]]
* [[:Category:Teams|Programming Teams List]]
* [[TI websites|TI Web Sites List]]

== Contributing ==

Please read our page on [[Contributing]] before you start contributing to WikiTI.

If you feel like contributing but do not know where, see the [[To Do List]].

86:Memory Mapping

2021-09-20T12:50:58Z

Zeroko: Fixed a link

[[Category:86:General Hardware Information|Memory Mapping]]
== Memory Mapping ==
Memory on the TI-86 is divided into pages of 16 KiB each. Addresses in the 4000-BFFFh range can be mapped to any page in any bank, while 0000-3FFFh is permanently mapped to ROM page 0, & C000-FFFFh is permanently mapped to RAM page 0.

Bits 0-5 of [[86:Ports:05|Port 05]] & [[86:Ports:06|Port 06]] select the page for the 4000-7FFFh & 8000-BFFFh ranges, respectively. These are output on external address lines 14-19 when the corresponding range is accessed. There are 4 memory banks, which can be chosen by bits 6-7 of these ports:
* 00: 256 KiB of ROM, divided into 16 pages. Port bits 4-5 (address bits 18-19) are unused, so ROM repeats 4 times.
* 01: 128 KiB of RAM, divided into 8 pages. Port bits 3-5 (address bits 17-19) are unused, so RAM repeats 8 times.
* 10: Unused.
* 11: Unused on mass-production TI-86es, or mirror of bank 00 on prototype TI-86es with flash ROM. The flash update code uses this bank for writing, in conjunction with bit 6 of [[86:Ports:04|Port 04]].
Each bank has its own /CE (chip enable) output, while all banks share a common /WE (write enable) output.

The memory mapping when a user program starts has port 05 set to 0Dh (a ROM page containing all the public ROM calls) & port 06 set to 41h (a RAM page containing the operation stack & the floating-point stack). The port 05 value must be restored before returning to the OS, but the port 06 value at exit is ignored.

== Unused Banks ==
Writing to ROM or to an unused bank has no effect. Reading from an unused bank will return the current bus content. This is generally the last byte of the instruction doing the reading, unless that instruction is interrupted by [[86:LCD_Controller#DMA|LCD DMA]], in which case it will be the last byte of the next LCD row to be displayed. However, if the bus is not updated for long enough (by reason of PC being in an unused bank while the LCD is turned off), the bits it reads will gradually decay to 0, causing it to execute various opcodes until it either transfers execution to a normal bank, HALTs, or gets stuck executing NOPs.

86:Ports:00

2021-09-20T12:48:44Z

Zeroko: Created page with "00 - LCD Base Address LCD Base Address == Synopsis == '''Port Number:''' 00h '''Function:''' LCD DMA Base Addre..."

[[Category:86:Ports:By_Address|00 - LCD Base Address]] [[Category:86:Ports:By_Name|LCD Base Address]]
== Synopsis ==
'''Port Number:''' 00h

'''Function:''' LCD DMA Base Address

This port controls the base address used as video memory by [[86:LCD_Controller#DMA|LCD DMA]].

=== Read Values ===
Because this port is write-only, its read behavior is the same as [[86:Memory_Mapping#Unused_Banks|Unused Banks]].

=== Write Values ===
* Bit 0-5: Bits 8-13 of LCD base address. The lower 8 bits of the address are always 0, & it is always in RAM page 0.
* Bit 6-7: Unused.

== Comments ==
* The OS sets this port to 7Ch, which results in video memory being accessible at FC00-FFFFh. However, it only sets it when the CPU is reset, so it should be set back to 7Ch (or 3Ch, BCh, or FCh, which behave identically) before returning to the OS.
* Changing this port causes the LCD image to change at the start (probably) of the next frame, so it can be used for double buffering, but not for a split screen effect.

86:Ports:04

2021-09-20T12:36:09Z

Zeroko: Created page with "04 - LCD Control LCD Control == Synopsis == '''Port Number:''' 04h '''Function:''' LCD Control, Memory Access C..."

[[Category:86:Ports:By_Address|04 - LCD Control]] [[Category:86:Ports:By_Name|LCD Control]]
== Synopsis ==
'''Port Number:''' 04h

'''Function:''' LCD Control, Memory Access Control

This port controls the [[86:LCD_Controller|LCD controller]] & access to RAM & ROM.

=== Read Values ===
Because this port is write-only, its read behavior is the same as [[86:Memory_Mapping#Unused_Banks|Unused Banks]].

=== Write Values ===
* Bit 0: Set 0 to enable CPU access to RAM. Set 1 to disable CPU access to RAM, in which case RAM behaves like an unused bank. [[86:LCD_Controller#DMA|DMA]] is still able to read from RAM normally when this bit is 1.
* Bit 1-2: Number of rows per logical frame. This also affects the LCD interrupt speed.
** 00: 16 rows & 4X interrupt speed.
** 01: 32 rows & 2X interrupt speed.
** 10: 48 rows & 4/3X interrupt speed.
** 11: 64 rows & normal interrupt speed.
* Bit 3-4: Number of columns per row to obtain via DMA.
** 00: 80 columns.
** 01: 96 columns (used by the TI-81).
** 10: 128 columns (used by the TI-85 & TI-86).
** 11: 160 columns (used by the PS-6600).
* Bit 5: Set 0 to use slower DMA (about 6 cycles per byte). Set 1 to use faster DMA (about 2 cycles per byte).
* Bit 6: Set 0 to enable writing to flash ROM. Set 1 to disable writing to flash ROM. On mass-production TI-86es, a missing AND gate results in the ROM behaving as if it were an unused bank if this is set to 0.
* Bit 7: Apparently unused.

== Comments ==
* The OS sets this port to 56h when the calculator is operating normally, & it uses 57h when the CPU is reset & when turning off. This appears to be intended either to save power or to protect the contents of RAM from accidental modification when the main batteries are low or are being changed.
* Setting fewer than 64 rows causes vertical repetition. It also makes the image darker.
* Setting fewer than 128 columns per row results in horizontal repetition in a pattern explained by [[86:LCD_Controller#DMA|DMA]].
* The OS uses the slower DMA mode. It is unknown whether the faster mode works on all calculators. The numbers of CPU cycles per byte are approximate because the LCD controller uses a separate clock from the CPU clock.
* Disabling access to RAM from within RAM is not recommended.
* Disabling access to ROM while the OS interrupt service routine is enabled is not recommended.

86:LCD Controller

2021-09-20T12:36:03Z

Zeroko: Created page with "LCD Controller The TI-86 has a memory-mapped STN liquid crystal display. The main portion of LCD controller is inside the ASIC, wi..."

[[Category:86:General Hardware Information|LCD Controller]]
The TI-86 has a memory-mapped STN liquid crystal display. The main portion of LCD controller is inside the ASIC, with row & column drivers & circuitry to produce the necessary voltages located on a daughterboard on which the LCD itself is also mounted.

== DMA ==
When the LCD is enabled, the ASIC needs to send pixels to it continuously. In order to allow the CPU to operate at the same time, the ASIC contains an internal buffer used to hold the pixels for the current row. This buffer is filled via DMA (direct memory access) that pauses the CPU once per row. This pause appears to be implemented internally by way of the Z80 signals /BUSREQ & /BUSACK, & as such, it is even able to occur in between the M cycles of a single instruction. No DMA is performed when the LCD is disabled.

The LCD always uses all 64 rows per physical frame. If the number of rows per logical frame is set lower than 64 via bits 1-2 of [[86:Ports:04|Port 4]], the subsequent logical frames are stacked vertically until the whole 64 rows are filled, with the last one being cut short if the rows per frame is set to 48. This stacking also makes the image darker, presumably because it increases the effective duty cycle.

The LCD controller always sends 160 pixels per row to the daughterboard, of which the first 80 & last 48 are visible on screen, for a total of 128 visible columns. However, DMA only reads as many bytes as necessary to contain the number of columns chosen via bits 3-4 of [[86:Ports:04|Port 4]]. Of the columns read via DMA, the first 80 are placed at the beginning of the buffer, & the remainder are placed at the end of the buffer. If this is fewer than the full 160 columns, the 4 columns immediately after the first 80 are copied from the last 4 of the previous row's DMA transfer. The remaining columns are copied starting from the beginning of the current row's DMA transfer.

== Interrupts ==
LCD interrupts occur twice per logical frame. They occur one row after one quarter & three quarters of the way down the frame, which is rows 17 & 49 (counting from 0) when set to 64 rows per frame. DMA occurs after the interrupt acknowledgement, which in particular is after the CPU reads the byte used to determine which offset to use for IM 2. The start of the interrupt service routine itself is then delayed until DMA finishes.

Warning: Toggling individual pixels every other interrupt may damage the LCD by causing a net charge to accumulate. Any given pixel's value should only be changed (at most) once every fourth interrupt. This is because the pixels of STN LCDs must be driven using AC waveforms to prevent damage due to charge buildup, & the calculator achieves this by alternating between 2 sets of voltages on consecutive frames.

86:Ports:02

2021-09-20T10:15:48Z

Zeroko: Created page with "02 - Contrast Contrast == Synopsis == '''Port Number:''' 02h '''Function:''' LCD Contrast This port controls t..."

[[Category:86:Ports:By_Address|02 - Contrast]] [[Category:86:Ports:By_Name|Contrast]]
== Synopsis ==
'''Port Number:''' 02h

'''Function:''' LCD Contrast

This port controls the LCD contrast.

=== Read Values ===
Because this port is write-only, its read behavior is the same as [[86:Memory_Mapping#Unused_Banks|Unused Banks]].

=== Write Values ===
* Bit 0-4: Contrast level. 00h is lightest & 1Fh is darkest.
* Bit 5-7: Unused.

== Comments ==
* In addition to writing to this port, the OS saves the current contrast at address C008h so that it is able to read it back later. If the value written to this port is different from the value at C008h, the value at C008h will be used the next time the user changes the contrast using the OS.
* If the value at C008h is greater than 1Fh, it is impossible to increase the contrast until it falls below 1Fh. Because the upper 3 bits are ignored by the hardware, this can result in having to cycle through all apparent contrast levels multiple times.

86:Memory Mapping

2021-09-20T09:22:30Z

Zeroko: Added section heading for unused banks

[[Category:86:General Hardware Information|Memory Mapping]]
== Memory Mapping ==
Memory on the TI-86 is divided into pages of 16 KiB each. Addresses in the 4000-BFFFh range can be mapped to any page in any bank, while 0000-3FFFh is permanently mapped to ROM page 0, & C000-FFFFh is permanently mapped to RAM page 0.

Bits 0-5 of [[86:Ports:05|Port 05]] & [[86:Ports:06|Port 06]] select the page for the 4000-7FFFh & 8000-BFFFh ranges, respectively. These are output on external address lines 14-19 when the corresponding range is accessed. There are 4 memory banks, which can be chosen by bits 6-7 of these ports:
* 00: 256 KiB of ROM, divided into 16 pages. Port bits 4-5 (address bits 18-19) are unused, so ROM repeats 4 times.
* 01: 128 KiB of RAM, divided into 8 pages. Port bits 3-5 (address bits 17-19) are unused, so RAM repeats 8 times.
* 10: Unused.
* 11: Unused on mass-production TI-86es, or mirror of bank 00 on prototype TI-86es with flash ROM. The flash update code uses this bank for writing, in conjunction with bit 6 of [[86:Ports:04|Port 04]].
Each bank has its own /CE (chip enable) output, while all banks share a common /WE (write enable) output.

The memory mapping when a user program starts has port 05 set to 0Dh (a ROM page containing all the public ROM calls) & port 06 set to 41h (a RAM page containing the operation stack & the floating-point stack). The port 05 value must be restored before returning to the OS, but the port 06 value at exit is ignored.

== Unused Banks ==
Writing to ROM or to an unused bank has no effect. Reading from an unused bank will return the current bus content. This is generally the last byte of the instruction doing the reading, unless that instruction is interrupted by [[86:LCD_DMA|LCD DMA]], in which case it will be the last byte of the next LCD row to be displayed. However, if the bus is not updated for long enough (by reason of PC being in an unused bank while the LCD is turned off), the bits it reads will gradually decay to 0, causing it to execute various opcodes until it either transfers execution to a normal bank, HALTs, or gets stuck executing NOPs.

86:Memory Mapping

2021-09-20T09:09:04Z

Zeroko: Created page with "Memory Mapping == Memory Mapping == Memory on the TI-86 is divided into pages of 16 KiB each. Addresses in the 4000-BFFFh range ca..."

[[Category:86:General Hardware Information|Memory Mapping]]
== Memory Mapping ==
Memory on the TI-86 is divided into pages of 16 KiB each. Addresses in the 4000-BFFFh range can be mapped to any page in any bank, while 0000-3FFFh is permanently mapped to ROM page 0, & C000-FFFFh is permanently mapped to RAM page 0.

Bits 0-5 of [[86:Ports:05|Port 05]] & [[86:Ports:06|Port 06]] select the page for the 4000-7FFFh & 8000-BFFFh ranges, respectively. These are output on external address lines 14-19 when the corresponding range is accessed. There are 4 memory banks, which can be chosen by bits 6-7 of these ports:
* 00: 256 KiB of ROM, divided into 16 pages. Port bits 4-5 (address bits 18-19) are unused, so ROM repeats 4 times.
* 01: 128 KiB of RAM, divided into 8 pages. Port bits 3-5 (address bits 17-19) are unused, so RAM repeats 8 times.
* 10: Unused.
* 11: Unused on mass-production TI-86es, or mirror of bank 00 on prototype TI-86es with flash ROM. The flash update code uses this bank for writing, in conjunction with bit 6 of [[86:Ports:04|Port 04]].
Each bank has its own /CE (chip enable) output, while all banks share a common /WE (write enable) output.

The memory mapping when a user program starts has port 05 set to 0Dh (a ROM page containing all the public ROM calls) & port 06 set to 41h (a RAM page containing the operation stack & the floating-point stack). The port 05 value must be restored before returning to the OS, but the port 06 value at exit is ignored.

Writing to ROM or to an unused bank has no effect. Reading from an unused bank will return the current bus content. This is generally the last byte of the instruction doing the reading, unless that instruction is interrupted by [[86:LCD_DMA|LCD DMA]], in which case it will be the last byte of the next LCD row to be displayed. However, if the bus is not updated for long enough (by reason of PC being in an unused bank while the LCD is turned off), the bits it reads will gradually decay to 0, causing it to execute various opcodes until it either transfers execution to a normal bank, HALTs, or gets stuck executing NOPs.

86:Ports:06

2021-09-20T09:08:52Z

Zeroko: Created page with "06 - Upper Memory Bank Upper Memory Bank == Synopsis == '''Port Number:''' 06h '''Function:''' Upper Memory Ban..."

[[Category:86:Ports:By_Address|06 - Upper Memory Bank]] [[Category:86:Ports:By_Name|Upper Memory Bank]]
== Synopsis ==
'''Port Number:''' 06h

'''Function:''' Upper Memory Bank Port

This port controls which memory bank is accessible in the 8000-BFFFh range. See [[86:Memory_Mapping|Memory Mapping]] for the interpretation of the banks & pages.

=== Read Values ===
* Bit 0-7: Reads last value written.

=== Write Values ===
* Bit 0-5: Page select (external address bits 14-19).
* Bit 6-7: Bank select.

== Comments ==
* This port is set to 41h when the OS passes control to a program. Its value at program exit is ignored.

86:Ports:05

2021-09-20T09:07:06Z

Zeroko: Fixed an incorrect link

[[Category:86:Ports:By_Address|05 - Lower Memory Bank]] [[Category:86:Ports:By_Name|Lower Memory Bank]]
== Synopsis ==
'''Port Number:''' 05h

'''Function:''' Lower Memory Bank Port

This port controls which memory bank is accessible in the 4000-7FFFh range. See [[86:Memory_Mapping|Memory Mapping]] for the interpretation of the banks & pages.

=== Read Values ===
* Bit 0-7: Reads last value written.

=== Write Values ===
* Bit 0-5: Page select (external address bits 14-19).
* Bit 6-7: Bank select.

== Comments ==
* This port is set to 0Dh when the OS passes control to a program.
* Set this port to 0Dh before attempting to call OS functions, because that page contains the public ROM call table. Also be sure to set it to 0Dh before returning to the OS.

86:Ports:05

2021-09-20T09:06:38Z

Zeroko: Created page with "05 - Lower Memory Bank Lower Memory Bank == Synopsis == '''Port Number:''' 05h '''Function:''' Lower Memory Ban..."

[[Category:86:Ports:By_Address|05 - Lower Memory Bank]] [[Category:86:Ports:By_Name|Lower Memory Bank]]
== Synopsis ==
'''Port Number:''' 05h

'''Function:''' Lower Memory Bank Port

This port controls which memory bank is accessible in the 4000-7FFFh range. See [[86:OS:Memory_Mapping|Memory Mapping]] for the interpretation of the banks & pages.

=== Read Values ===
* Bit 0-7: Reads last value written.

=== Write Values ===
* Bit 0-5: Page select (external address bits 14-19).
* Bit 6-7: Bank select.

== Comments ==
* This port is set to 0Dh when the OS passes control to a program.
* Set this port to 0Dh before attempting to call OS functions, because that page contains the public ROM call table. Also be sure to set it to 0Dh before returning to the OS.

86:Ports:07

2021-09-20T07:15:51Z

Zeroko: Created page with "07 - Link Link == Synopsis == '''Port Number:''' 07h '''Function:''' Link Port This port controls the calculat..."

[[Category:86:Ports:By_Address|07 - Link]] [[Category:86:Ports:By_Name|Link]]
== Synopsis ==
'''Port Number:''' 07h

'''Function:''' Link Port

This port controls the calculator's serial link port. It is a GPIO port that is wired to open-collector drivers connected to the jack's tip & ring, with the sleeve connected to ground.

=== Read Values ===
* Bit 0: Tip (red wire) state.
* Bit 1: Ring (white wire) state.
* Bit 2-3: Reads last value written.
* Bit 4-7: Unused.

=== Write Values ===
* Bit 0: Unused if bit 4 is 0. Should be set to 0 if bits 2 & 4 are both set to 1.
* Bit 1: Unused if bit 5 is 0. Should be set to 0 if bits 3 & 5 are both set to 1.
* Bit 2: Set 0 to let other device control the tip. Set 1 to pull the tip voltage low.
* Bit 3: Set 0 to let other device control the ring. Set 1 to pull the ring voltage low.
* Bit 4: Set 0 to configure bit 0 for input. Set 1 to configure bit 0 for output. This is always set to the same value as bit 2 by the OS, but always 0 has the same effect.
* Bit 5: Set 0 to configure bit 1 for input. Set 1 to configure bit 1 for output. This is always set to the same value as bit 3 by the OS, but always 0 has the same effect.
* Bit 6-7: Controls direction for bits 2-3. Should always be set to 1 (output).

== Comments ==
* Be sure to set this port to C0h before using OS functions that check the link (including getKey) & before returning to the OS, or it will be confused by what it sees as a silent link attempt.
* While the TI-86 uses 5 V as its high level, linking with suitably-designed 3.3 V open-collector circuitry (such as in TI's 68K-based calculators) also works.

86:Ports:03

2021-09-20T06:24:11Z

Zeroko: Typo in category link

[[Category:86:Ports:By_Address|03 - Interrupt Control]] [[Category:86:Ports:By_Name|Interrupt Control]]
== Synopsis ==
'''Port Number:''' 03h

'''Function:''' Interrupt Control Port

This port controls all devices that can generate interrupts.

=== Read Values ===
* Bit 0: Set if the ON key generated an interrupt.
* Bit 1: Set if the LCD controller generated an interrupt (after DMA for rows 17 & 49). Used by the OS as a periodic interrupt source (approximately 200 Hz).
* Bit 2: Set if the /INT pin generated an interrupt (unused on the TI-86).
* Bit 3: Reset if the ON key is being pressed; set otherwise.
* Bit 4-7: Unused.

=== Write Values ===
* Bit 0: Set 0 to disable ON key interrupts and to acknowledge an ON key interrupt. Set 1 to enable ON key interrupts.
* Bit 1: Set 0 to disable LCD controller interrupts & to acknowledge an interrupt from the LCD controller. Set 1 to enable interrupts from the first timer.
* Bit 2: Set 0 to disable external interrupts & to acknowledge an external interrupt. Set 1 to enable external interrupts.
* Bit 3: Set 0 to turn off the LCD. Set 1 to turn on the LCD.
* Bit 4-7: Unused.

== Comments ==
* You need to acknowledge interrupts. Otherwise a new interrupt will be generated directly after you enable interrupts again with EI. Because that disables that particular interrupt at the same time, you may have to write a second value to this port to re-enable it.
* The OS shuts down by turning off the LCD & HALTing with the ON key interrupt enabled.

86:Ports:03

2021-09-20T06:23:06Z

Zeroko: Based on 83Plus:Ports:03

[[Category:86:Ports:By_Address|06 - Interrupt Control]] [[Category:86:Ports:By_Name|Interrupt Control]]
== Synopsis ==
'''Port Number:''' 03h

'''Function:''' Interrupt Control Port

This port controls all devices that can generate interrupts.

=== Read Values ===
* Bit 0: Set if the ON key generated an interrupt.
* Bit 1: Set if the LCD controller generated an interrupt (after DMA for rows 17 & 49). Used by the OS as a periodic interrupt source (approximately 200 Hz).
* Bit 2: Set if the /INT pin generated an interrupt (unused on the TI-86).
* Bit 3: Reset if the ON key is being pressed; set otherwise.
* Bit 4-7: Unused.

=== Write Values ===
* Bit 0: Set 0 to disable ON key interrupts and to acknowledge an ON key interrupt. Set 1 to enable ON key interrupts.
* Bit 1: Set 0 to disable LCD controller interrupts & to acknowledge an interrupt from the LCD controller. Set 1 to enable interrupts from the first timer.
* Bit 2: Set 0 to disable external interrupts & to acknowledge an external interrupt. Set 1 to enable external interrupts.
* Bit 3: Set 0 to turn off the LCD. Set 1 to turn on the LCD.
* Bit 4-7: Unused.

== Comments ==
* You need to acknowledge interrupts. Otherwise a new interrupt will be generated directly after you enable interrupts again with EI. Because that disables that particular interrupt at the same time, you may have to write a second value to this port to re-enable it.
* The OS shuts down by turning off the LCD & HALTing with the ON key interrupt enabled.

84PCE:Ports:E000

2021-05-06T19:59:38Z

Zeroko: Added divisor latch

[[Category:84PCE:Ports:By_Address|E000 - ARM Coprocessor]] [[Category:84PCE:Ports:By_Name|ARM Coprocessor]]
== Synopsis ==
'''Port Number:''' E000-EFFF

'''Memory-mapped Address:''' F90000

'''Function:''' ARM Coprocessor

This appears to be an FTUART010 (which is 16550A-compatible), & is connected to the ARM coprocessor on Python Edition. The 16550 register layout (see [https://www.lammertbies.nl/comm/info/serial-uart], for example) works after multiplying its offsets by 4.

{|-
|Port   
|Direction   
|Information   
|-
|E000
|Read
Write

Read Write
|Receive Holding Register (when bit 7 of E00C is 0)
Transmit Holding Register (when bit 7 of E00C is 0)

Divisor Latch LSB (when bit 7 of E00C is 1)
|-
|E004
|Read Write
Read Write
|Interrupt Enable Register (when bit 7 of E00C is 0)
Divisor Latch MSB (when bit 7 of E00C is 1)
|-
|E008
|Read
Write
|Interupt Status Register
FIFO Control Register
|-
|E00C
|Read Write
|Line Control Register
|-
|E010
|Read Write
|Modem Control Register
|-
|E014
|Read
|Line Status Register
|-
|E018
|Read
|Modem Status Register
|-
|E01C
|Read Write
|Scratchpad Register
|-
|E068
|Read
|01? (not from 16550)
|-
|E06C
|Read
|01? (not from 16550)
|-
|E070
|Read
|10? (not from 16550)
|-
|}

84PCE:Ports:E000

2021-05-06T00:35:46Z

Zeroko: Updated based on FTUART010

[[Category:84PCE:Ports:By_Address|E000 - ARM Coprocessor]] [[Category:84PCE:Ports:By_Name|ARM Coprocessor]]
== Synopsis ==
'''Port Number:''' E000-EFFF

'''Memory-mapped Address:''' F90000

'''Function:''' ARM Coprocessor

This appears to be an FTUART010 (which is 16550A-compatible), & is connected to the ARM coprocessor on Python Edition. The 16550 register layout (see [https://www.lammertbies.nl/comm/info/serial-uart], for example) works after multiplying its offsets by 4.

{|-
|Port   
|Direction   
|Information   
|-
|E000
|Read
Write
|Receive Holding Register
Transmit Holding Register
|-
|E004
|Read Write
|Interrupt Enable Register
|-
|E008
|Read
Write
|Interupt Status Register
FIFO Control Register
|-
|E00C
|Read Write
|Line Control Register
|-
|E010
|Read Write
|Modem Control Register
|-
|E014
|Read
|Line Status Register
|-
|E018
|Read
|Modem Status Register
|-
|E01C
|Read Write
|Scratchpad Register
|-
|E068
|Read
|01? (not from 16550)
|-
|E06C
|Read
|01? (not from 16550)
|-
|E070
|Read
|10? (not from 16550)
|-
|}

84PCE:Wait States

2021-02-23T06:51:28Z

Zeroko: Detailed timing for LCD controller

[[Category:84PCE:General_Hardware_Information|Wait States]]
== Synopsis ==
The eZ80 processor is able to perform a memory access in a single cycle. However, on the TI-84+CE, accesses will actually take longer due to wait states. For example, a read from RAM will take 4 cycles, because it has 3 wait states. The wait states for parallel Flash accesses can be customized, but it is unknown whether that is the case for other memory regions or for the newer serial flash.

== Flash Access Wait States ==

=== Parallel Flash ===
Calculators produced prior to revision M use a parallel flash chip. These chips are limited to a maximum read rate under 20 MHz, necessitating at least 1 wait state for the ASIC's faster 48 MHz clock. The ASIC's internal memory mapping hardware adds a minimum of 5 wait states just to ferry the request to the flash chip and the response back to the CPU, but additional external wait states are required for the flash chip to make its reply. See [[84PCE:Ports:1005]] for more information.

=== Serial Flash ===
Calculators produced starting in 2019 with revision M no longer use a parallel flash chip, but instead an SPI flash chip. This flash chip needs much longer to initially retrieve data from a random address, but can stream sequential data at a reasonable rate. A new ASIC design takes advantage of this capability by adding a cache between the flash chip and CPU.

According to tests performed by [[User:Jacobly|Jacobly]], the cache is 8 K in size, structured as a 2-way set associative cache with 128 sets of 32 bytes chosen by address bits 5-11. A fetch from the same cache line as previously accessed costs 1 wait state (so the read takes a total of 2 cycles), a fetch from a different cache line costs 2 wait states, and a cache miss costs 194-200 wait states.

Code execution from flash displays high locality of reference, so amortized performance should be reasonably good, although the 200 cycle penalty for a cache miss probably hurts a fair bit. For flash-resident data files, programmers should try to organize them to keep related data together to maximize cache utilization. A good access pattern can make accessing data in flash twice as fast as getting it from RAM, while a bad pattern can make it substantially worse than even pulling it from the old parallel flash.

== LCD DMA ==
The LCD controller uses Direct Memory Access to retrieve the pixels from RAM. However, since the CPU and the LCD controller cannot access RAM at the same time, there are some waitstates caused asynchronously by the DMA during RAM accesses. The rate of waitstates caused by the DMA appears to be directly proportional to the rate of data being sent to the screen, so lower bit-per-pixel modes will reduce the general performance hit.

== Wait State Layout ==
{|-
|Address Range   
|Read   
|Write   
|Description   
|-
|000000-3FFFFF
|5+
|Crash
|[[84PCE:Ports:1000|Parallel flash]]: Wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. The OS sets a total of 9 wait states.
|-
|000000-3FFFFF
|1-200
|Crash
|[[84PCE:OS:Serial_Flash_Commands|Serial flash:]] See above discussion.
|-
|400000-7FFFFF
|257
|Crash
|Parallel flash: Unmapped address space. Can be mapped to Flash using [[:84PCE:Ports:1002|1002]], after which Flash wait states are active.
|-
|400000-BFFFFF
|1-200
|Crash
|Serial flash: Flash mirrors. Appears to be subject to flash cache timing as discussed above
|-
|800000-CFFFFF
|257
|257
|Parallel flash: Unmapped address space.
|-
|C00000-CFFFFF
|1
|1
|Serial flash: Unmapped address space.
|-
|D00000-D3FFFF
|3
|1
|RAM
|-
|D40000-D657FF
|3
|1
|VRAM
|-
|D65800-D72BFF
|3
|1
|Unmapped address space. Reads garbage.
|-
|D72C00-D7FFFF
|3
|1
|Unmapped address space. Reads garbage (revisions up to at least C) or mirror of D52C00-D5FFFF (at least I+).
|-
|D80000-DFFFFF
|3
|1
|Mirror of D00000-D7FFFF
|-
|Not mapped
|1
|1
|Port range [[:84PCE:Ports:0000|0000]] (mirrored every 0100 bytes)
|-
|E00000-E0FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:1000|1000]] (mirrored every 0100 bytes)
|-
|E10000-E1FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:2000|2000]] (mirrored every 0100 bytes)
|-
|E20000-E2FFFF
|3

9-12

6-8

5-6

4-5
|3

9-12

6-8

5-6

4-5
|Memory-mapped port range [[:84PCE:Ports:3000|3000]] (mirrored every 0200 bytes)

Extra cycles if bit 7 ''or'' 8 of the address is set, when cpu is running at 48 MHz.

Same at 24 MHz.

Same at 12 MHz.

Same at 6 MHz.
|-
|E30000-E3FFFF
|2

2

2

2

2

3

1

1

1

1
|1

20-21/22

15/13

11

9

3

15-16/13

12/10

10/8

8
|Memory-mapped port range [[:84PCE:Ports:4000|4000]] (mirrored every 1000 bytes)

Special timing for 4000-400F & 4018-401B (pre-M/M+) at 48 MHz

Same at 24 MHz

Same at 12 MHz

Same at 6 MHz

Special timing for 4200-43FF (any CPU speed)

Special timing for 4C00-4DFF (pre-M/M+) at 48 MHz

Same at 24 MHz

Same at 12 MHz

Same at 6 MHz
|-
|E40000-EFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-
|F00000-F0FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:5000|5000]] (mirrored every 0100 bytes)
|-
|F10000-F1FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:6000|6000]] (mirrored every 0020 bytes)
|-
|F20000-F2FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:7000|7000]] (mirrored every 0100 bytes)
|-
|F30000-F3FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:8000|8000]] (mirrored every 0080 bytes)
|-
|F40000-F4FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:9000|9000]] (mirrored every 1000 bytes, possibly protected port range)
|-
|F50000-F5FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:A000|A000]] (mirrored every 0080 bytes)
|-
|F60000-F6FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:B000|B000]] (mirrored every 1000 bytes)
|-
|F70000-F7FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:C000|C000]] (mirrored every 0100 bytes)
|-
|F80000-F8FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:D000|D000]] (mirrored every 0080 bytes)
|-
|F90000-F9FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:E000|E000]] (mirrored every 0080 bytes)
|-
|FA0000-FAFFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:F000|F000]] (mirrored every 0100 bytes)
|-
|FB0000-FEFFFF
|2
|2
|Unmapped port range (reads all zeros)
|-
|FF0000-FFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-}

84PCE:Wait States

2021-02-21T08:28:12Z

Zeroko: F000 mirroring

[[Category:84PCE:General_Hardware_Information|Wait States]]
== Synopsis ==
The eZ80 processor is able to perform a memory access in a single cycle. However, on the TI-84+CE, accesses will actually take longer due to wait states. For example, a read from RAM will take 4 cycles, because it has 3 wait states. The wait states for parallel Flash accesses can be customized, but it is unknown whether that is the case for other memory regions or for the newer serial flash.

== Flash Access Wait States ==

=== Parallel Flash ===
Calculators produced prior to revision M use a parallel flash chip. These chips are limited to a maximum read rate under 20 MHz, necessitating at least 1 wait state for the ASIC's faster 48 MHz clock. The ASIC's internal memory mapping hardware adds a minimum of 5 wait states just to ferry the request to the flash chip and the response back to the CPU, but additional external wait states are required for the flash chip to make its reply. See [[84PCE:Ports:1005]] for more information.

=== Serial Flash ===
Calculators produced starting in 2019 with revision M no longer use a parallel flash chip, but instead an SPI flash chip. This flash chip needs much longer to initially retrieve data from a random address, but can stream sequential data at a reasonable rate. A new ASIC design takes advantage of this capability by adding a cache between the flash chip and CPU.

According to tests performed by [[User:Jacobly|Jacobly]], the cache is 8 K in size, structured as a 2-way set associative cache with 128 sets of 32 bytes chosen by address bits 5-11. A fetch from the same cache line as previously accessed costs 1 wait state (so the read takes a total of 2 cycles), a fetch from a different cache line costs 2 wait states, and a cache miss costs 194-200 wait states.

Code execution from flash displays high locality of reference, so amortized performance should be reasonably good, although the 200 cycle penalty for a cache miss probably hurts a fair bit. For flash-resident data files, programmers should try to organize them to keep related data together to maximize cache utilization. A good access pattern can make accessing data in flash twice as fast as getting it from RAM, while a bad pattern can make it substantially worse than even pulling it from the old parallel flash.

== LCD DMA ==
The LCD controller uses Direct Memory Access to retrieve the pixels from RAM. However, since the CPU and the LCD controller cannot access RAM at the same time, there are some waitstates caused asynchronously by the DMA during RAM accesses. The rate of waitstates caused by the DMA appears to be directly proportional to the rate of data being sent to the screen, so lower bit-per-pixel modes will reduce the general performance hit.

== Wait State Layout ==
{|-
|Address Range   
|Read   
|Write   
|Description   
|-
|000000-3FFFFF
|5+
|Crash
|[[84PCE:Ports:1000|Parallel flash]]: Wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. The OS sets a total of 9 wait states.
|-
|000000-3FFFFF
|1-200
|Crash
|[[84PCE:OS:Serial_Flash_Commands|Serial flash:]] See above discussion.
|-
|400000-7FFFFF
|257
|Crash
|Parallel flash: Unmapped address space. Can be mapped to Flash using [[:84PCE:Ports:1002|1002]], after which Flash wait states are active.
|-
|400000-BFFFFF
|1-200
|Crash
|Serial flash: Flash mirrors. Appears to be subject to flash cache timing as discussed above
|-
|800000-CFFFFF
|257
|257
|Parallel flash: Unmapped address space.
|-
|C00000-CFFFFF
|1
|1
|Serial flash: Unmapped address space.
|-
|D00000-D3FFFF
|3
|1
|RAM
|-
|D40000-D657FF
|3
|1
|VRAM
|-
|D65800-D72BFF
|3
|1
|Unmapped address space. Reads garbage.
|-
|D72C00-D7FFFF
|3
|1
|Unmapped address space. Reads garbage (revisions up to at least C) or mirror of D52C00-D5FFFF (at least I+).
|-
|D80000-DFFFFF
|3
|1
|Mirror of D00000-D7FFFF
|-
|Not mapped
|1
|1
|Port range [[:84PCE:Ports:0000|0000]] (mirrored every 0100 bytes)
|-
|E00000-E0FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:1000|1000]] (mirrored every 0100 bytes)
|-
|E10000-E1FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:2000|2000]] (mirrored every 0100 bytes)
|-
|E20000-E2FFFF
|3

9-12

6-8

5-6

4-5
|3

9-12

6-8

5-6

4-5
|Memory-mapped port range [[:84PCE:Ports:3000|3000]] (mirrored every 0200 bytes)

Extra cycles if bit 7 ''or'' 8 of the address is set, when cpu is running at 48Mhz.

Same at 24Mhz.

Same at 12Mhz.

Same at 6Mhz.
|-
|E30000-E3FFFF
|2
|1
|Memory-mapped port range [[:84PCE:Ports:4000|4000]] (mirrored every 1000 bytes)
|-
|E40000-EFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-
|F00000-F0FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:5000|5000]] (mirrored every 0100 bytes)
|-
|F10000-F1FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:6000|6000]] (mirrored every 0020 bytes)
|-
|F20000-F2FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:7000|7000]] (mirrored every 0100 bytes)
|-
|F30000-F3FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:8000|8000]] (mirrored every 0080 bytes)
|-
|F40000-F4FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:9000|9000]] (mirrored every 1000 bytes, possibly protected port range)
|-
|F50000-F5FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:A000|A000]] (mirrored every 0080 bytes)
|-
|F60000-F6FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:B000|B000]] (mirrored every 1000 bytes)
|-
|F70000-F7FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:C000|C000]] (mirrored every 0100 bytes)
|-
|F80000-F8FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:D000|D000]] (mirrored every 0080 bytes)
|-
|F90000-F9FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:E000|E000]] (mirrored every 0080 bytes)
|-
|FA0000-FAFFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:F000|F000]] (mirrored every 0100 bytes)
|-
|FB0000-FEFFFF
|2
|2
|Unmapped port range (reads all zeros)
|-
|FF0000-FFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-}

84PCE:Ports:0005

2021-02-21T07:57:44Z

Zeroko: (Mostly) not unknown

[[Category:84PCE:Ports:By_Address|0005 - Port access controls]]
== Synopsis ==
'''Port Number:''' 0005

'''Function:''' Controls access to ports & the backlight PWM.

== Details ==

This port enables access to various parts of the ASIC.

=== Bit [0] ===
Enables access to [[84PCE:Ports:F000|F000]] port range.

=== Bit [1] ===
Enables access to [[84PCE:Ports:E000|E000]] port range (ARM coprocessor).

=== Bit [2] ===
Enables access to [[84PCE:Ports:D000|D000]] port range (LCD SPI).

=== Bit [3] ===
Latches value written, no apparent effect.

=== Bit [4] ===
Enables access to [[84PCE:Ports:B000_Unknowns|B000]] port range (backlight).

=== Bit [5] ===
Enables writes to [[84PCE:Ports:A000|A000]] port range (keypad). When disabled, read access still succeeds.

=== Bit [6] ===
Enables the backlight PWM. When disabled, the screen will be fully dark or bright, depending on which part of the PWM cycle it was in when last enabled.

=== Bit [7] ===
Writes have no apparent effect, value does not latch.

84PCE:Ports:0006

2021-02-21T05:52:52Z

Zeroko: Updated effect of bits 0 & 1 on port access (oops)

[[Category:84PCE:Ports:By_Address|0006 - Unknown]]
== Synopsis ==
'''Port Number:''' 0006

'''Function:''' Unknown

== Details ==

This port seems to affect the display refresh.

=== Bit [0] ===
Latches value written, OS defaults this to set. Resetting this bit reduces current consumption by about 3 mA, so it does ''something.'' When reset, the [[84PCE:Ports:3000|USB controller ports]] cannot be accessed.

=== Bit [1] ===
Reset this bit to disable display upadates. When reset, the [[84PCE:Ports:4000|LCD controller ports]] also cannot be accessed.

=== Bit [2] ===
Set this bit to enable display updates if bit 1 is ever reset. ???

This bit is known to unlock protected ports, such as [[84PCE:Ports:2000|SHA256]],
and enables the [[84PCE:Ports:0028#Bit_.5B3.5D|flash unlock sequence]].
It is cleared every time the boot code interrupt handler runs.

=== Bit [3] ===
Writes do not latch; no apparent effect.

Used by OS on Python Edition.

=== Bit [4] ===
<s>Flash lock status.</s>

=== Bits [7:3] ===
Writes do not latch; no apparent effect.

84PCE:Ports:0006

2021-02-21T05:40:01Z

Zeroko: Updated effect of bits 0 & 1 on port access

[[Category:84PCE:Ports:By_Address|0006 - Unknown]]
== Synopsis ==
'''Port Number:''' 0006

'''Function:''' Unknown

== Details ==

This port seems to affect the display refresh.

=== Bit [0] ===
Latches value written, OS defaults this to set. Resetting this bit reduces current consumption by about 3 mA, so it does ''something.'' When reset, the [[84PCE:Ports:3000|USB controller ports]] cannot be written & read as 20 0E 3E 00, repeating every 4 bytes.

=== Bit [1] ===
Reset this bit to disable display upadates. When reset, the [[84PCE:Ports:4000|LCD controller ports]] cannot be written & read as B1 00 00 00 (revision C) or 2D 09 00 00 (revision N), repeating every 4 bytes.

=== Bit [2] ===
Set this bit to enable display updates if bit 1 is ever reset. ???

This bit is known to unlock protected ports, such as [[84PCE:Ports:2000|SHA256]],
and enables the [[84PCE:Ports:0028#Bit_.5B3.5D|flash unlock sequence]].
It is cleared every time the boot code interrupt handler runs.

=== Bit [3] ===
Writes do not latch; no apparent effect.

Used by OS on Python Edition.

=== Bit [4] ===
<s>Flash lock status.</s>

=== Bits [7:3] ===
Writes do not latch; no apparent effect.

84PCE:Ports:Control

2021-02-21T05:25:58Z

Zeroko: Updated port 000D

[[Category:84PCE:Ports:By_Address|Control]] [[Category:84PCE:Ports:By_Name|Control]]
== Synopsis ==
'''Port Number:''' 0000-0fff

'''Function:''' Master Control

This port range is used to configure and control important things; possibly the reason why it does not have a memory-mapped address. It is mirrored every 0x100 bytes.

If a port is not listed; it indicates that writes have no effect and do not latch, and that reads are 0. Note that this may not be true one hundred percent.

== Port Address Space ==

{|-
|Port   
|Default   
|Information   
|-
|[[:84PCE:Ports:0000|0000]]
|03
|CPU Speed Control
|-
|[[:84PCE:Ports:0001|0001]]
|03
|OS Timer Control
|-
|[[:84PCE:Ports:0002|0002]]
|
|Read only, value can change
|-
|[[:84PCE:Ports:0003|0003]]
|00
|Hardware ID
|-
|[[:84PCE:Ports:0005|0005]]
|76
|Set bit 5 to freeze, bit 6 affects backlight
|-
|[[:84PCE:Ports:0006|0006]]
|03
|Display refresh
|-
|[[:84PCE:Ports:0007|0007]]
|B7
|Latches values written
|-
|[[:84PCE:Ports:0008|0008]]
|7F
|Cannot change value
|-
|[[:84PCE:Ports:0009|0009]]
|37
|Power control system
|-
|[[:84PCE:Ports:000A|000A]]
|FD
|Latches value written
|-
|[[:84PCE:Ports:000B|000B]]
|F8
|Charging Status
|-
|[[:84PCE:Ports:000C|000C]]
|00
|Latches value written
|-
|[[:84PCE:Ports:000D|000D]]
|FF
|Power control
|-
|[[:84PCE:Ports:000E|000E]]
|0A
|Latches value written
|-
|[[:84PCE:Ports:000F|000F]]
|42
|High nibble may be a status, low 2 bits latch value written
|-
|[[:84PCE:Ports:001C|001C]]
|80
|Cannot change value
|-
|[[:84PCE:Ports:001D|001D]]
|A7
|Privileged address
|-
|[[:84PCE:Ports:0020|0020]]
|7C
|Memory protection
|-
|[[:84PCE:Ports:0028|0028]]
|
|Bit 1 is always 0
|-
|[[:84PCE:Ports:0029|0029]]
|00
|Bit 0 latches value written
|-
|[[:84PCE:Ports:002A|002A]]
|70
|Latches value written
|-
|[[:84PCE:Ports:002B|002B]]
|FE
|Latches value written
|-
|[[:84PCE:Ports:002C|002C]]
|
|Ports 002C-0031 latch value written
|-
|[[:84PCE:Ports:0032|0032]]
|
|Latches value written
|-
|[[:84PCE:Ports:0033|0033]]
|
|Latches value written
|-
|[[:84PCE:Ports:0034|0034]]
|
|Latches value written
|-
|[[:84PCE:Ports:0035|0035]]
|
|Latches value written
|-
|[[:84PCE:Ports:0036|0036]]
|
|Ports 0036-0039 latch value written
|-
|}

84PCE:Ports:000D

2021-02-21T05:23:23Z

Zeroko: Created page with "000D - Power control == Synopsis == '''Port Number:''' 000D '''Function:''' Power control == Details == This port enables power to vario..."

[[Category:84PCE:Ports:By_Address|000D - Power control]]
== Synopsis ==
'''Port Number:''' 000D

'''Function:''' Power control

== Details ==

This port enables power to various parts of the ASIC. Each region reads as 0 when unpowered.

=== Bit [0] ===
[[84PCE:Ports:3000|USB controller]] power. Resets when unpowered. Returning to the OS without reinitializing causes it to freeze while USB is connected.

=== Bit [1] ===
[[84PCE:Ports:4000|LCD controller]] power. Resets when unpowered. The LCD does not update until the controller is initialized properly.

=== Bit [2] ===
Power for RAM range D20000-D3FFFF. When unpowered, its content is quickly randomized.

=== Bit [3] ===
Power for VRAM range D40000-D7FFFF. When unpowered, its content is quickly randomized.

=== Bits [4:7] ===
Writes have no effect. These bits read as 1 if the subsystems controlled by the corresponding bits in 0-3 are receiving power. There is a slight delay between changing bits 0-3 & these changing in response.

84PCE:Wait States

2021-02-07T00:59:01Z

Zeroko: VRAM mirroring in unmapped space updated

[[Category:84PCE:General_Hardware_Information|Wait States]]
== Synopsis ==
The eZ80 processor is able to perform a memory access in a single cycle. However, on the TI-84+CE, accesses will actually take longer due to wait states. For example, a read from RAM will take 4 cycles, because it has 3 wait states. The wait states for parallel Flash accesses can be customized, but it is unknown whether that is the case for other memory regions or for the newer serial flash.

== Flash Access Wait States ==

=== Parallel Flash ===
Calculators produced prior to revision M use a parallel flash chip. These chips are limited to a maximum read rate under 20 MHz, necessitating at least 1 wait state for the ASIC's faster 48 MHz clock. The ASIC's internal memory mapping hardware adds a minimum of 5 wait states just to ferry the request to the flash chip and the response back to the CPU, but additional external wait states are required for the flash chip to make its reply. See [[84PCE:Ports:1005]] for more information.

=== Serial Flash ===
Calculators produced starting in 2019 with revision M no longer use a parallel flash chip, but instead an SPI flash chip. This flash chip needs much longer to initially retrieve data from a random address, but can stream sequential data at a reasonable rate. A new ASIC design takes advantage of this capability by adding a cache between the flash chip and CPU.

According to tests performed by [[User:Jacobly|Jacobly]], the cache is 8 K in size, structured as a 2-way set associative cache with 128 sets of 32 bytes chosen by address bits 5-11. A fetch from the same cache line as previously accessed costs 1 wait state (so the read takes a total of 2 cycles), a fetch from a different cache line costs 2 wait states, and a cache miss costs 194-200 wait states.

Code execution from flash displays high locality of reference, so amortized performance should be reasonably good, although the 200 cycle penalty for a cache miss probably hurts a fair bit. For flash-resident data files, programmers should try to organize them to keep related data together to maximize cache utilization. A good access pattern can make accessing data in flash twice as fast as getting it from RAM, while a bad pattern can make it substantially worse than even pulling it from the old parallel flash.

== LCD DMA ==
The LCD controller uses Direct Memory Access to retrieve the pixels from RAM. However, since the CPU and the LCD controller cannot access RAM at the same time, there are some waitstates caused asynchronously by the DMA during RAM accesses. The rate of waitstates caused by the DMA appears to be directly proportional to the rate of data being sent to the screen, so lower bit-per-pixel modes will reduce the general performance hit.

== Wait State Layout ==
{|-
|Address Range   
|Read   
|Write   
|Description   
|-
|000000-3FFFFF
|5+
|Crash
|[[84PCE:Ports:1000|Parallel flash]]: Wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. The OS sets a total of 9 wait states.
|-
|000000-3FFFFF
|1-200
|Crash
|[[84PCE:OS:Serial_Flash_Commands|Serial flash:]] See above discussion.
|-
|400000-7FFFFF
|257
|Crash
|Parallel flash: Unmapped address space. Can be mapped to Flash using [[:84PCE:Ports:1002|1002]], after which Flash wait states are active.
|-
|400000-BFFFFF
|1-200
|Crash
|Serial flash: Flash mirrors. Appears to be subject to flash cache timing as discussed above
|-
|800000-CFFFFF
|257
|257
|Parallel flash: Unmapped address space.
|-
|C00000-CFFFFF
|1
|1
|Serial flash: Unmapped address space.
|-
|D00000-D3FFFF
|3
|1
|RAM
|-
|D40000-D657FF
|3
|1
|VRAM
|-
|D65800-D72BFF
|3
|1
|Unmapped address space. Reads garbage.
|-
|D72C00-D7FFFF
|3
|1
|Unmapped address space. Reads garbage (revisions up to at least C) or mirror of D52C00-D5FFFF (at least I+).
|-
|D80000-DFFFFF
|3
|1
|Mirror of D00000-D7FFFF
|-
|Not mapped
|1
|1
|Port range [[:84PCE:Ports:0000|0000]] (mirrored every 0100 bytes)
|-
|E00000-E0FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:1000|1000]] (mirrored every 0100 bytes)
|-
|E10000-E1FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:2000|2000]] (mirrored every 0100 bytes)
|-
|E20000-E2FFFF
|3

9-12

6-8

5-6

4-5
|3

9-12

6-8

5-6

4-5
|Memory-mapped port range [[:84PCE:Ports:3000|3000]] (mirrored every 0200 bytes)

Extra cycles if bit 7 ''or'' 8 of the address is set, when cpu is running at 48Mhz.

Same at 24Mhz.

Same at 12Mhz.

Same at 6Mhz.
|-
|E30000-E3FFFF
|2
|1
|Memory-mapped port range [[:84PCE:Ports:4000|4000]] (mirrored every 1000 bytes)
|-
|E40000-EFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-
|F00000-F0FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:5000|5000]] (mirrored every 0100 bytes)
|-
|F10000-F1FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:6000|6000]] (mirrored every 0020 bytes)
|-
|F20000-F2FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:7000|7000]] (mirrored every 0100 bytes)
|-
|F30000-F3FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:8000|8000]] (mirrored every 0080 bytes)
|-
|F40000-F4FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:9000|9000]] (mirrored every 1000 bytes, possibly protected port range)
|-
|F50000-F5FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:A000|A000]] (mirrored every 0080 bytes)
|-
|F60000-F6FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:B000|B000]] (mirrored every 1000 bytes)
|-
|F70000-F7FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:C000|C000]] (mirrored every 0100 bytes)
|-
|F80000-F8FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:D000|D000]] (mirrored every 0080 bytes)
|-
|F90000-F9FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:E000|E000]] (mirrored every 0080 bytes)
|-
|FA0000-FAFFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:F000|F000]] (reads all zeros)
|-
|FB0000-FEFFFF
|2
|2
|Unmapped port range (reads all zeros)
|-
|FF0000-FFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-}

Category:84PCE:RAM:By Address

2021-02-07T00:58:01Z

Zeroko: (VRAM mirroring in unmapped space updated)

See also [[:Category:84PCE:RAM:By Name|list of RAM areas by name]].

Please read our page on [[Contributing]] before editing these pages!

The eZ80 has a 24-bit linear address space. Layout:
* 000000h: Start of flash. The first 128 K are locked boot sectors. The first 8 are divided into 8 K sectors, all of which are locked. The certificate is now a single 64 K sector, so I hope you don't crash while rebuilding it.
* 000066h: Flash exception handler. Write-to-flash without permission triggers the non-maskable interrupt to fire.
* 00007Eh: Hardware/Emu flag: This byte indicates whether the ROM is a hardware ROM or emulator.
* 000080h: Start of boot code jump table.
* 020000h: Start of OS.
* 0C0000h: Start of user archive.
* 3B0000h: Certificate.
* 3C0000h: Temp RAM backup, on newer versions of TIOS debug output is also written here.
* 3E0000h: Temp RAM backup.
* 3F0000h: Temp RAM backup, temp certificate backup, swap sector.
* 400000h: Can be setup to mirror flash, but usually unmapped.
* 800000h: Always unmapped.
* D00000h: Start of RAM. 256 K.
* D1A87Eh: Top of the SPL stack.
* D1A881h: Start of UserMem.
* D40000h: Start of VRAM. 320x240x2 bytes = 153600 bytes.
* D65800h: Unmapped memory.
* D72C00h: Unmapped memory (revisions up to at least C) or mirror of D52C00h (at least I+).
* D80000h: Mirror of D00000h.
* E00000h: Start of [[84PCE:Wait_States|memory-mapped I/O]] address spaces.

SafeRAM Areas:
* D031F6h: [[84PCE:RAM:D031F6|pixelShadow]] - 8400 bytes
* D052C6h: [[84PCE:RAM:D052C6|pixelShadow2]] - 8400 bytes
* D07396h: [[84PCE:RAM:D07396|cmdPixelShadow]] - 8400 bytes
* D09466h: [[84PCE:RAM:D09466|plotSScreen]] - 21945 bytes
* D0EA1Fh: [[84PCE:RAM:D0EA1F|saveSScreen]] - 21945 bytes
** Note that the above is contiguous, which provides a total linear free space of 69090 bytes of RAM.
** [[84PCE:RAM:D052C6|pixelShadow2]] is the most stable; and is a viable option for ''testing'' TSRs and hooks.

More SafeRAM Areas:
* D006C0h: [[84PCE:RAM:D006C0|textShadow]] - 260 bytes
* D0232Dh: [[84PCE:RAM:D0232D|cmdShadow]] - 260 bytes

Also, if you do not wish to use the LCD cursor (This is not RAM, but can be used as scrap)
* E30800h: cursorImage - 1024 bytes
[[Category:84PCE:RAM|RAM Areas by Address]]

84PCE:Wait States

2021-01-28T17:03:03Z

Zeroko: VRAM mirroring in unmapped space updated

[[Category:84PCE:General_Hardware_Information|Wait States]]
== Synopsis ==
The eZ80 processor is able to perform a memory access in a single cycle. However, on the TI-84+CE, accesses will actually take longer due to wait states. For example, a read from RAM will take 4 cycles, because it has 3 wait states. The wait states for parallel Flash accesses can be customized, but it is unknown whether that is the case for other memory regions or for the newer serial flash.

== Flash Access Wait States ==

=== Parallel Flash ===
Calculators produced prior to revision M use a parallel flash chip. These chips are limited to a maximum read rate under 20 MHz, necessitating at least 1 wait state for the ASIC's faster 48 MHz clock. The ASIC's internal memory mapping hardware adds a minimum of 5 wait states just to ferry the request to the flash chip and the response back to the CPU, but additional external wait states are required for the flash chip to make its reply. See [[84PCE:Ports:1005]] for more information.

=== Serial Flash ===
Calculators produced starting in 2019 with revision M no longer use a parallel flash chip, but instead an SPI flash chip. This flash chip needs much longer to initially retrieve data from a random address, but can stream sequential data at a reasonable rate. A new ASIC design takes advantage of this capability by adding a cache between the flash chip and CPU.

According to tests performed by [[User:Jacobly|Jacobly]], the cache is 8 K in size, structured as a 2-way set associative cache with 128 sets of 32 bytes chosen by address bits 5-11. A fetch from the same cache line as previously accessed costs 1 wait state (so the read takes a total of 2 cycles), a fetch from a different cache line costs 2 wait states, and a cache miss costs 194-200 wait states.

Code execution from flash displays high locality of reference, so amortized performance should be reasonably good, although the 200 cycle penalty for a cache miss probably hurts a fair bit. For flash-resident data files, programmers should try to organize them to keep related data together to maximize cache utilization. A good access pattern can make accessing data in flash twice as fast as getting it from RAM, while a bad pattern can make it substantially worse than even pulling it from the old parallel flash.

== LCD DMA ==
The LCD controller uses Direct Memory Access to retrieve the pixels from RAM. However, since the CPU and the LCD controller cannot access RAM at the same time, there are some waitstates caused asynchronously by the DMA during RAM accesses. The rate of waitstates caused by the DMA appears to be directly proportional to the rate of data being sent to the screen, so lower bit-per-pixel modes will reduce the general performance hit.

== Wait State Layout ==
{|-
|Address Range   
|Read   
|Write   
|Description   
|-
|000000-3FFFFF
|5+
|Crash
|[[84PCE:Ports:1000|Parallel flash]]: Wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. The OS sets a total of 9 wait states.
|-
|000000-3FFFFF
|1-200
|Crash
|[[84PCE:OS:Serial_Flash_Commands|Serial flash:]] See above discussion.
|-
|400000-7FFFFF
|257
|Crash
|Parallel flash: Unmapped address space. Can be mapped to Flash using [[:84PCE:Ports:1002|1002]], after which Flash wait states are active.
|-
|400000-BFFFFF
|1-200
|Crash
|Serial flash: Flash mirrors. Appears to be subject to flash cache timing as discussed above
|-
|800000-CFFFFF
|257
|257
|Parallel flash: Unmapped address space.
|-
|C00000-CFFFFF
|1
|1
|Serial flash: Unmapped address space.
|-
|D00000-D3FFFF
|3
|1
|RAM
|-
|D40000-D657FF
|3
|1
|VRAM
|-
|D65800-D72BFF
|3
|1
|Unmapped address space. Reads garbage.
|-
|D72C00-D7FFFF
|3
|1
|Unmapped address space. Reads garbage (revisions up to at least C) or mirror of D52C00-D5FFFF (at least L+).
|-
|D80000-DFFFFF
|3
|1
|Mirror of D00000-D7FFFF
|-
|Not mapped
|1
|1
|Port range [[:84PCE:Ports:0000|0000]] (mirrored every 0100 bytes)
|-
|E00000-E0FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:1000|1000]] (mirrored every 0100 bytes)
|-
|E10000-E1FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:2000|2000]] (mirrored every 0100 bytes)
|-
|E20000-E2FFFF
|3

9-12

6-8

5-6

4-5
|3

9-12

6-8

5-6

4-5
|Memory-mapped port range [[:84PCE:Ports:3000|3000]] (mirrored every 0200 bytes)

Extra cycles if bit 7 ''or'' 8 of the address is set, when cpu is running at 48Mhz.

Same at 24Mhz.

Same at 12Mhz.

Same at 6Mhz.
|-
|E30000-E3FFFF
|2
|1
|Memory-mapped port range [[:84PCE:Ports:4000|4000]] (mirrored every 1000 bytes)
|-
|E40000-EFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-
|F00000-F0FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:5000|5000]] (mirrored every 0100 bytes)
|-
|F10000-F1FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:6000|6000]] (mirrored every 0020 bytes)
|-
|F20000-F2FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:7000|7000]] (mirrored every 0100 bytes)
|-
|F30000-F3FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:8000|8000]] (mirrored every 0080 bytes)
|-
|F40000-F4FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:9000|9000]] (mirrored every 1000 bytes, possibly protected port range)
|-
|F50000-F5FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:A000|A000]] (mirrored every 0080 bytes)
|-
|F60000-F6FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:B000|B000]] (mirrored every 1000 bytes)
|-
|F70000-F7FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:C000|C000]] (mirrored every 0100 bytes)
|-
|F80000-F8FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:D000|D000]] (mirrored every 0080 bytes)
|-
|F90000-F9FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:E000|E000]] (mirrored every 0080 bytes)
|-
|FA0000-FAFFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:F000|F000]] (reads all zeros)
|-
|FB0000-FEFFFF
|2
|2
|Unmapped port range (reads all zeros)
|-
|FF0000-FFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-}

Category:84PCE:RAM:By Address

2021-01-28T17:03:02Z

Zeroko: VRAM mirroring in unmapped space updated

See also [[:Category:84PCE:RAM:By Name|list of RAM areas by name]].

Please read our page on [[Contributing]] before editing these pages!

The eZ80 has a 24-bit linear address space. Layout:
* 000000h: Start of flash. The first 128 K are locked boot sectors. The first 8 are divided into 8 K sectors, all of which are locked. The certificate is now a single 64 K sector, so I hope you don't crash while rebuilding it.
* 000066h: Flash exception handler. Write-to-flash without permission triggers the non-maskable interrupt to fire.
* 00007Eh: Hardware/Emu flag: This byte indicates whether the ROM is a hardware ROM or emulator.
* 000080h: Start of boot code jump table.
* 020000h: Start of OS.
* 0C0000h: Start of user archive.
* 3B0000h: Certificate.
* 3C0000h: Temp RAM backup, on newer versions of TIOS debug output is also written here.
* 3E0000h: Temp RAM backup.
* 3F0000h: Temp RAM backup, temp certificate backup, swap sector.
* 400000h: Can be setup to mirror flash, but usually unmapped.
* 800000h: Always unmapped.
* D00000h: Start of RAM. 256 K.
* D1A87Eh: Top of the SPL stack.
* D1A881h: Start of UserMem.
* D40000h: Start of VRAM. 320x240x2 bytes = 153600 bytes.
* D65800h: Unmapped memory.
* D72C00h: Unmapped memory (revisions up to at least C) or mirror of D52C00h (at least L+).
* D80000h: Mirror of D00000h.
* E00000h: Start of [[84PCE:Wait_States|memory-mapped I/O]] address spaces.

SafeRAM Areas:
* D031F6h: [[84PCE:RAM:D031F6|pixelShadow]] - 8400 bytes
* D052C6h: [[84PCE:RAM:D052C6|pixelShadow2]] - 8400 bytes
* D07396h: [[84PCE:RAM:D07396|cmdPixelShadow]] - 8400 bytes
* D09466h: [[84PCE:RAM:D09466|plotSScreen]] - 21945 bytes
* D0EA1Fh: [[84PCE:RAM:D0EA1F|saveSScreen]] - 21945 bytes
** Note that the above is contiguous, which provides a total linear free space of 69090 bytes of RAM.
** [[84PCE:RAM:D052C6|pixelShadow2]] is the most stable; and is a viable option for ''testing'' TSRs and hooks.

More SafeRAM Areas:
* D006C0h: [[84PCE:RAM:D006C0|textShadow]] - 260 bytes
* D0232Dh: [[84PCE:RAM:D0232D|cmdShadow]] - 260 bytes

Also, if you do not wish to use the LCD cursor (This is not RAM, but can be used as scrap)
* E30800h: cursorImage - 1024 bytes
[[Category:84PCE:RAM|RAM Areas by Address]]

Category:84PCE:RAM:By Address

2021-01-28T07:14:17Z

Zeroko: VRAM mirroring in unmapped address space on L-N

See also [[:Category:84PCE:RAM:By Name|list of RAM areas by name]].

Please read our page on [[Contributing]] before editing these pages!

The eZ80 has a 24-bit linear address space. Layout:
* 000000h: Start of flash. The first 128 K are locked boot sectors. The first 8 are divided into 8 K sectors, all of which are locked. The certificate is now a single 64 K sector, so I hope you don't crash while rebuilding it.
* 000066h: Flash exception handler. Write-to-flash without permission triggers the non-maskable interrupt to fire.
* 00007Eh: Hardware/Emu flag: This byte indicates whether the ROM is a hardware ROM or emulator.
* 000080h: Start of boot code jump table.
* 020000h: Start of OS.
* 0C0000h: Start of user archive.
* 3B0000h: Certificate.
* 3C0000h: Temp RAM backup, on newer versions of TIOS debug output is also written here.
* 3E0000h: Temp RAM backup.
* 3F0000h: Temp RAM backup, temp certificate backup, swap sector.
* 400000h: Can be setup to mirror flash, but usually unmapped.
* 800000h: Always unmapped.
* D00000h: Start of RAM. 256 K.
* D1A87Eh: Top of the SPL stack.
* D1A881h: Start of UserMem.
* D40000h: Start of VRAM. 320x240x2 bytes = 153600 bytes.
* D65800h: Unmapped memory.
* D72C00h: Unmapped memory (revisions up to at least C) or mirror of D52C00h (at least L through N).
* D80000h: Mirror of D00000h.
* E00000h: Start of [[84PCE:Wait_States|memory-mapped I/O]] address spaces.

SafeRAM Areas:
* D031F6h: [[84PCE:RAM:D031F6|pixelShadow]] - 8400 bytes
* D052C6h: [[84PCE:RAM:D052C6|pixelShadow2]] - 8400 bytes
* D07396h: [[84PCE:RAM:D07396|cmdPixelShadow]] - 8400 bytes
* D09466h: [[84PCE:RAM:D09466|plotSScreen]] - 21945 bytes
* D0EA1Fh: [[84PCE:RAM:D0EA1F|saveSScreen]] - 21945 bytes
** Note that the above is contiguous, which provides a total linear free space of 69090 bytes of RAM.
** [[84PCE:RAM:D052C6|pixelShadow2]] is the most stable; and is a viable option for ''testing'' TSRs and hooks.

More SafeRAM Areas:
* D006C0h: [[84PCE:RAM:D006C0|textShadow]] - 260 bytes
* D0232Dh: [[84PCE:RAM:D0232D|cmdShadow]] - 260 bytes

Also, if you do not wish to use the LCD cursor (This is not RAM, but can be used as scrap)
* E30800h: cursorImage - 1024 bytes
[[Category:84PCE:RAM|RAM Areas by Address]]

84PCE:Wait States

2021-01-28T07:10:55Z

Zeroko: VRAM mirroring in unmapped address space on L-N

[[Category:84PCE:General_Hardware_Information|Wait States]]
== Synopsis ==
The eZ80 processor is able to perform a memory access in a single cycle. However, on the TI-84+CE, accesses will actually take longer due to wait states. For example, a read from RAM will take 4 cycles, because it has 3 wait states. The wait states for parallel Flash accesses can be customized, but it is unknown whether that is the case for other memory regions or for the newer serial flash.

== Flash Access Wait States ==

=== Parallel Flash ===
Calculators produced prior to revision M use a parallel flash chip. These chips are limited to a maximum read rate under 20 MHz, necessitating at least 1 wait state for the ASIC's faster 48 MHz clock. The ASIC's internal memory mapping hardware adds a minimum of 5 wait states just to ferry the request to the flash chip and the response back to the CPU, but additional external wait states are required for the flash chip to make its reply. See [[84PCE:Ports:1005]] for more information.

=== Serial Flash ===
Calculators produced starting in 2019 with revision M no longer use a parallel flash chip, but instead an SPI flash chip. This flash chip needs much longer to initially retrieve data from a random address, but can stream sequential data at a reasonable rate. A new ASIC design takes advantage of this capability by adding a cache between the flash chip and CPU.

According to tests performed by [[User:Jacobly|Jacobly]], the cache is 8 K in size, structured as a 2-way set associative cache with 128 sets of 32 bytes chosen by address bits 5-11. A fetch from the same cache line as previously accessed costs 1 wait state (so the read takes a total of 2 cycles), a fetch from a different cache line costs 2 wait states, and a cache miss costs 194-200 wait states.

Code execution from flash displays high locality of reference, so amortized performance should be reasonably good, although the 200 cycle penalty for a cache miss probably hurts a fair bit. For flash-resident data files, programmers should try to organize them to keep related data together to maximize cache utilization. A good access pattern can make accessing data in flash twice as fast as getting it from RAM, while a bad pattern can make it substantially worse than even pulling it from the old parallel flash.

== LCD DMA ==
The LCD controller uses Direct Memory Access to retrieve the pixels from RAM. However, since the CPU and the LCD controller cannot access RAM at the same time, there are some waitstates caused asynchronously by the DMA during RAM accesses. The rate of waitstates caused by the DMA appears to be directly proportional to the rate of data being sent to the screen, so lower bit-per-pixel modes will reduce the general performance hit.

== Wait State Layout ==
{|-
|Address Range   
|Read   
|Write   
|Description   
|-
|000000-3FFFFF
|5+
|Crash
|[[84PCE:Ports:1000|Parallel flash]]: Wait states are controlled by [[:84PCE:Ports:1005|1005]], adding to the minimum of 5. The OS sets a total of 9 wait states.
|-
|000000-3FFFFF
|1-200
|Crash
|[[84PCE:OS:Serial_Flash_Commands|Serial flash:]] See above discussion.
|-
|400000-7FFFFF
|257
|Crash
|Parallel flash: Unmapped address space. Can be mapped to Flash using [[:84PCE:Ports:1002|1002]], after which Flash wait states are active.
|-
|400000-BFFFFF
|1-200
|Crash
|Serial flash: Flash mirrors. Appears to be subject to flash cache timing as discussed above
|-
|800000-CFFFFF
|257
|257
|Parallel flash: Unmapped address space.
|-
|C00000-CFFFFF
|1
|1
|Serial flash: Unmapped address space.
|-
|D00000-D3FFFF
|3
|1
|RAM
|-
|D40000-D657FF
|3
|1
|VRAM
|-
|D65800-D72BFF
|3
|1
|Unmapped address space. Reads garbage.
|-
|D72C00-D7FFFF
|3
|1
|Unmapped address space. Reads garbage (revisions up to at least C) or mirror of D52C00-D5FFFF (at least revisions L through N).
|-
|D80000-DFFFFF
|3
|1
|Mirror of D00000-D7FFFF
|-
|Not mapped
|1
|1
|Port range [[:84PCE:Ports:0000|0000]] (mirrored every 0100 bytes)
|-
|E00000-E0FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:1000|1000]] (mirrored every 0100 bytes)
|-
|E10000-E1FFFF
|1
|1
|Memory-mapped port range [[:84PCE:Ports:2000|2000]] (mirrored every 0100 bytes)
|-
|E20000-E2FFFF
|3

9-12

6-8

5-6

4-5
|3

9-12

6-8

5-6

4-5
|Memory-mapped port range [[:84PCE:Ports:3000|3000]] (mirrored every 0200 bytes)

Extra cycles if bit 7 ''or'' 8 of the address is set, when cpu is running at 48Mhz.

Same at 24Mhz.

Same at 12Mhz.

Same at 6Mhz.
|-
|E30000-E3FFFF
|2
|1
|Memory-mapped port range [[:84PCE:Ports:4000|4000]] (mirrored every 1000 bytes)
|-
|E40000-EFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-
|F00000-F0FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:5000|5000]] (mirrored every 0100 bytes)
|-
|F10000-F1FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:6000|6000]] (mirrored every 0020 bytes)
|-
|F20000-F2FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:7000|7000]] (mirrored every 0100 bytes)
|-
|F30000-F3FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:8000|8000]] (mirrored every 0080 bytes)
|-
|F40000-F4FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:9000|9000]] (mirrored every 1000 bytes, possibly protected port range)
|-
|F50000-F5FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:A000|A000]] (mirrored every 0080 bytes)
|-
|F60000-F6FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:B000|B000]] (mirrored every 1000 bytes)
|-
|F70000-F7FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:C000|C000]] (mirrored every 0100 bytes)
|-
|F80000-F8FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:D000|D000]] (mirrored every 0080 bytes)
|-
|F90000-F9FFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:E000|E000]] (mirrored every 0080 bytes)
|-
|FA0000-FAFFFF
|2
|2
|Memory-mapped port range [[:84PCE:Ports:F000|F000]] (reads all zeros)
|-
|FB0000-FEFFFF
|2
|2
|Unmapped port range (reads all zeros)
|-
|FF0000-FFFFFF
|1
|1
|Unmapped port range (reads all zeros)
|-}

84PCE:Ports:D000

2020-04-08T21:07:05Z

Zeroko: Updated based on FTSSP010 driver for Linux

[[Category:84PCE:Ports:By_Address|D000 - SPI]] [[Category:84PCE:Ports:By_Name|SPI]]
== Synopsis ==
'''Port Number:''' D000

'''Memory-mapped Address:''' F80000

'''Function:''' LCD Interface

This appears to be an FTSSP010 or compatible SPI controller that interfaces with the LCD. Non-extended commands from [https://cdn-shop.adafruit.com/datasheets/ILI9340.pdf] appear to work, but there's plenty of unknown commands used by the boot code.

{|-
|Port   
|Default   
|Bits   
|Information   
|-
|D000 F80000
|
|0000F38C
|CR0: Boot code writes 180B/09 before/after turning on/off the lcd.
|-
|D004 F80004
|0000182B
|007FFFFF
|CR1: Boot code initializes to 02000B. Bits 0-15 are clock divider - 1, bits 16-23 are data length - 1, and bits 24-31 are padding length.
|-
|D008 F80008
|0002000B
|00000F8F
|CR2: Boot code initializes to 010C. Bit 0 is set to transfer data. Bit 7 is set/reset for reading/writing.
|-
|D00C F8000C
|
|000007F6
|Status bits. Bit 2 is set if data is being sent or received and bits 12-15 are the number of bits queued. Boot code waits for bits 2 and 12-15 to be 0 before/after reading/writing.
|-
|D010 F80010
|00002100
|
|Interrupt control.
|-
|D014 F80014
|00000008
|
|Interrupt status.
|-
|D018 F80018
|
|
|FIFO in/out.
|-
|D01C F8001C
|0E0F0F1F
|
|Inside reserved range. Appears to be a copy of the feature register at D064.
|-
|D060 F80060
|00012100
|
|Revision (read-only)
|-
|D064 F80064
|0E0F0F1F
|
|Features (read-only): 32-bit data width, 16-bit FIFOs, list of extra protocols supported.
|}

== Known Commands ==
{|-
|Hex Defaults
|Command
|Details
|-
|01
|Software Reset
|
|-
|10 10
|Enable Sleep Mode
|Turns pixels black, low power mode?
|-
|11 11
|Disable Sleep Mode
|
|-
|12
|Enable Partial Mode
|Resets vertical scrolling start to 0.
|-
|13
|Disable Partial Mode
|Also disables vertical scrolling mode and resets vertical scrolling start to 0.
|-
|20
|Uninvert Colors
|
|-
|21
|Invert Colors
|
|-
|26 <8:GC> 26 00 26 02
|Set Gamma
|Selects between 4 preset gamma curves: Valid values are 1, 2, 4, 8, invalid values appear to use 1.
|-
|28
|Turn Off Display
|Turns all pixels white.
|-
|29 29
|Turn On Display
|Restore GRAM pixels.
|-
|2A <BE16:StartCol> <BE16:EndCol> 2A 0000 013F
|Set Window Columns
|Set the pixel update window from StartCol to EndCol inclusive.
|-
|2B <BE16:StartLine> <BE16:EndRow> 2B 0000 00EF
|Set Window Rows
|Set the pixel update window from StartRow to EndRow inclusive.
|-
|30 <BE16:StartRow> <BE16:EndRow>
|Set Partial Area Rows
|Only displays from StartRow to EndRow inclusive, other lines white.
|-
|33 <BE16:TopArea> <BE16:ScrollArea> <BE16:BottomArea>
|Vertical Scrolling Definition
|TopArea/BottomArea are static (non-scrolling) line counts before and after the ScrollArea whose value is ignored.
|-
|36 <8:MAC> 36 08
|Memory Address Control
|Bit 2: Horizontal Refresh Order Bit 3: BGR Order Bit 4: Vertical Refresh Order Bit 5: Column Major Update Bit 6: Column Update Order Bit 7: Row Update Order
|-
|37 <BE16:VSP>
|Vertical Scrolling Start Position
|First line of ScrollArea starts at this GRAM line.
|-
|38
|Disable Idle Mode
|Restore 18bpp mode.
|-
|39
|Enable Idle Mode
|3bpp 8 color mode (only uses msb of each color component).
|-
|3A ? 3A 66
|Interface Pixel Format
|Upper and lower nibbles are modes for the two interfaces: 3 is 12bpp, 5 is 16bpp, 6 is 18bpp (msb is ignored, invalid uses 18bpp).
|-
|B0 ? ? B0 11 F0
|Interface Control
|First Param: Bit 0: Use lcd controller clocks instead of internal clocks. Bit 4: Get GRAM data from lcd controller instead of spi interface. Bit 7: Bypass GRAM and output directly to lcd. Second Param: Polarity of clocks?
|-
|B1 ? ? ? B1 01 05 14 B1 01 15 14
|Unknown?
|
|-
|B2 ? ? ? ? ? B2 0C 0C 00 33 33
|Unknown?
|
|-
|B7 ? B7 35
|Unknown?
|
|-
|-
|BB ? BB 17 BB 1B
|Unknown?
|
|-
|C0 ? C0 2C C0 22
|Unknown?
|
|-
|C2 ? C2 01
|Unknown?
|
|-
|C3 ? C3 03 C3 15
|Unknown?
|
|-
|C4 ? C4 20
|Unknown?
|
|-
|C6 ? C6 0F
|Unknown?
|
|-
|D0 ? ? D0 AF A1
|Unknown?
|
|-
|D2 ? D2 00
|Unknown?
|
|-
|DC
|Unknown?
|One parameter "read" and checked if equal to 0x35, but reading doesn't appear to work in the first place...
|-
|E0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? E0 D0 00 00 10 0F 1A 2D 54 3F 3B 18 17 13 17 E0 D0 00 00 10 0F 1A 2D 54 3F 3B 18 17 13 17
|Positive Gamma Correction
|Definitely affects gamma, parameters unknown and don't match docs.
|-
|E1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? E1 D0 00 00 10 0F 09 2B 43 40 3B 18 17 13 17 E1 D0 00 00 10 0F 09 2B 43 40 3B 18 17 13 17
|Negative Gamma Correction
|Definitely affects gamma, parameters unknown and don't match docs.
|-
|E9 ? ? ? E9 08 08 08
|Unknown?
|-
|EB
|Something!
|-
|F0
|Gamma?
|-
|F1
|Gamma?
|-
|F2
|Gamma?
|}

== Example ==

=== Sending ===
<nowiki> ld a,036h ; Flips the lcd horizontally, vertically, and swaps the b and r components
call spiCmd
ld a,0C0h
call spiParam

ld a,002h ; Resetting the lcd on exit
call spiCmd
jp boot_InitializeHardware

; Input: A = parameter
spiParam:
scf ; First bit is set for data
.db 030h ; jr nc,? ; skips over one byte
; Input: A = command
spiCmd:
or a,a ; First bit is clear for commands
ld hl,0F80818h
call spiWrite
ld l,h
ld (hl),001h
spiWait:
ld l,00Dh
spiWait1:
ld a,(hl)
and a,0F0h
jr nz,spiWait1
dec l
spiWait2:
bit 2,(hl)
jr nz,spiWait2
ld l,h
ld (hl),a
ret
spiWrite:
ld b,3
spiWriteLoop:
rla
rla
rla
ld (hl),a ; send 3 bits
djnz spiWriteLoop
ret</nowiki>

=== Receiving ===

'''This does not appear to work, always returning 0 on the calcs I've tested, due to either a TI bug or hardware issue.'''

<nowiki>; Input: A = command
; Ouput: A = data
spiRead:
ld hl,0F80808
ld (hl),00Ch
ld l,018h
or a,a
call spiWrite
xor a,a ; not sure what this is for
call spiWrite
ld l,009h
ld (hl),001h
dec l
ld (hl),081h
call spiWait
ld l,$18
ld a,(hl) ; dummy read
ld a,(hl)
ld a,(hl) ; Why is there no wait after dummy read?
ld a,(hl)
rla
rla
rla
rla
rla
and a,0E0h
ld c,a
ld a,(hl)
rla
rla
and a,01Ch
or a,c
ld c,a
ld a,(hl)
rra ; why are we throwing away the lsb instead of the msb
and a,003h
or a,c
ret</nowiki>