View source for 84PCE:Ports:4000

[[Category:84PCE:Ports:By_Address|4000 - LCD Controller]] [[Category:84PCE:Ports:By_Name|LCD Controller]]
== Synopsis ==
'''Port Number:''' 4000

'''Memory-mapped address:''' E30000

'''Function:''' LCD Controller

The ports in this range are for accessing the LCD controller. With these ports, you can configure the LCD DMA address, change the color mode, access the palette, alter the LCD cursor, and possibly other useful things.

Datasheet: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0293c/DDI0293.pdf

The LCD itself appears to be the Giant GPM1421C0. Datasheet: http://beck-oled-lcd-tft-display.de/fileadmin/giant-plus/GPM1421C0.pdf

== PL111 Register Summary ==
{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! TIOS Value
! Description
|-
| LCDTiming0
| 0x000
| R/W
| 0x00000000
| Horizontal Axis Panel Control Register
|}
 <nowiki>TIOS Default:
0x1F0A0338

HBP = 31 (actual =        HBP + 1 =  32)
HFP = 10 (actual =        HFP + 1 =  11)
HSW =  3 (actual =        HSW + 1 =   4)
PPL = 14 (actual = 16 * (PPL + 1) = 240)</nowiki>
<br>
{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDTiming1
| 0x004
| R/W
| 0x00000000
| Vertical Axis Panel Control Register
|}
 <nowiki>TIOS Default:
0x0402093F

VBP =   4
VFP =   2
VSW =   2 (actual = VSW + 1 =   3)
LPP = 319 (actual = LPP + 1 = 320)</nowiki>
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDTiming2
| 0x008
| R/W
| 0x00000000
| Clock and Signal Polarity Control Register
|}
 <nowiki>TIOS Default:
0x0402093F

PCD =   2
BCD =   0
CPL = 239
IOE =   1
IPC =   1
IHS =   1
IVS =   1
ACB =   0
CLKSEL = 0</nowiki>
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDTiming3
| 0x00C
| R/W
| 0x00000
| Line End Control Register
|}
 <nowiki>TIOS Default:
0x00000000

LEE = 0
LED = 0</nowiki>
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDUPBASE
| 0x010
| R/W
| 0x00000000
| Upper Panel Frame Base Address Register, i.e. LCD VRAM address. Only bits 8-18 have an effect; the address is masked into the 0xD00000-0xD7FF00 range.
|}
 <nowiki>TIOS Default:
0x00D40000</nowiki>
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDLPBASE
| 0x014
| R/W
| 0x00000000
| Lower Panel Frame Base Address Register, N/A
|}
 <nowiki>TIOS Default:
0x00000000</nowiki>
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDControl
| 0x018
| R/W
| 0x0000
| LCD Control Register
|}
This Register controls the operating mode, and the panel pixel parameters<br>
 <nowiki>31----------------------------------------------------------------------------------------------0
UNDEFINDED      WTRMRK UN LCDVCMP LCDPWR BEPO BEBO BGR LCDDUAL LCDMONO8 LCDTFT LCDBW LCDBPP LCDEN
000000000000000 0      00 00      0      0    0    0   0       0        0      0     000    0

TIOS Default:
000000000000000 0      00 00      1      0    0    1   0       0        1      0     110    1

UNDEFINDED	= Undefined

WTRMRK		= LCD DMA FIFO watermark level

UN		= Undefined

LCDVCMP		= Generate interrupt at:
		    b00 = start of vertical synchronization
		    b01 = start of back porch
		    b10 = start of active video
		    b11 = start of front porch

LCDPWR		= LCD power enable:
		    0 = power not gated through to LCD panel and CLD[23:0] signals disabled, (held LOW)
		    1 = power gated through to LCD panel and CLD[23:0] signals enabled, (active)

BEPO		= Big-endian pixel ordering within a byte:
		    0 = little-endian ordering within a byte
		    1 = big-endian pixel ordering within a byte

BEBO		= Big-endian byte order:
		    0 = little-endian byte order
		    1 = big-endian byte order

BGR		= RGB or BGR format selection:
		    0 = RGB normal output
		    1 = BGR red and blue swapped

LCDDUAL		= LCD interface is dual-panel STN:
		    0 = single-panel LCD is in use
		    1 = dual-panel LCD is in use

LCDMONO8	= Monochrome LCD. This has an 8-bit interface. This bit controls whether monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes, and you must program it to zero
		    0 = mono LCD uses 4-bit interface
		    1 = mono LCD uses 8-bit interface

LCDTFT		= LCD is TFT:
		    0 = LCD is an STN display. Use gray scaler
		    1 = LCD is a TFT display. Do not use gray scaler

LCDBW		= STN LCD is monochrome (black and white):
		    0 = STN LCD is color
		    1 = STN LCD is monochrome

LCDBPP		= LCD bits per pixel:
		    b000 = 1bpp
		    b001 = 2bpp
		    b010 = 4bpp
		    b011 = 8bpp
		    b100 = 16bpp
		    b101 = 24bpp (TFT panel only)
		    b110 = 16bpp 5:6:5 mode
		    b111 = 12bpp 4:4:4 mode

LCDEN		= CLCDC enable:
		    0 = LCD signals CLLP, CLCP, CLFP, CLAC, and CLLE disabled (LOW)
		    1 = LCD signals CLLP, CLCP, CLFP, CLAC, and CLLE enabled (HIGH)</nowiki>
To set the LCD to 8bpp (palette mode):
 <nowiki>ld a,$27
ld ($E30018),a</nowiki>

When the LCD is in 8bpp mode, data written to VRAM will act as an 8-bit index to the LCD's 256x16-bit Color Palette. Note that the colour palette must be initialized prior to setting this mode or you will receive unexpected results. (See LCDPalette register - 0x200 for information on the Color Palette).<br>
This will effectively halve the amount of VRAM required to store a full resolution 320x240 image (76800 bytes vs 153600 bytes). The extra 76800 bytes of VRAM could be used to double buffer or for temporary data storage.<br>
Note that the TIOS will not be usable in this mode, it expects 16bpp 5:6:5 mode at all times.<br>

To set the LCD to 16bpp 5:6:5 mode (TIOS default):
 <nowiki>ld a,$2D
ld ($E30018),a</nowiki>
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDIMSC
| 0x01C
| R/W
| 0x0
| Interrupt Mask Set/Clear Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDRIS
| 0x020
| RO
| 0x0
| Raw Interrupt Status Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDMIS
| 0x024
| RO
| 0x0
| Masked Interrupt Status Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDICR
| 0x028
| WO
| 0x0
| LCD Interrupt Clear Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDUPCURR
| 0x02C
| RO
| 0x00000000
| LCD Upper and Lower Panel Current Address Value Registers
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDLPCURR
| 0x030
| RO
| 0x00000000
| LCD Upper and Lower Panel Current Address Value Registers
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| -
| 0x034-0x1FC
| -
| -
| Reserved
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| LCDPalette
| 0x200-0x3FC
| R/W
| 0x00000000
| 256x16-bit Color Palette Registers
|}
The LCDPalette Registers contain 256 palette entries.
 <nowiki>15-----------------0
I  BLUE  GREEN RED
0  00000 00000 00000

I		= Intensity/unused
B		= Blue palette data
G		= Green palette data
R		= Red palette data</nowiki>

The palette can hold 256 x 16-bit colour entries in 1555 format. The BLUE and RED values can be swapped via bit-8 of the LCDControl Register.<br>
<br>
When 8bpp mode is enabled the LCD will utilize graphics data to index this palette and display the resultant colour - as opposed to interpreting graphics data as colours directly.<br>
Palettes can be very useful for reducing data requirements and increasing display related performance.
<br>
To generate and copy a palette of low=high (xLIBC equivilent) colours converted to 1555 format, you can do something similar to:
 <nowiki>CopyHL1555Palette:
	ld hl,$E30200				; palette mem
	ld b,0
_cp1555loop:
	ld d,b
	ld a,b
	and %11000000
	srl d
	rra
	ld e,a
	ld a,%00011111
	and b
	or e
	ld (hl),a
	inc hl
	ld (hl),d
	inc hl
	inc b
	jr nz,_cp1555loop
	ret</nowiki>
With this palette installed, high=low graphics data (from the TI-84+CSE for example) can be reused without the need for conversion. This is because the high=low colour data will now become an index to the converted 1555 palette. Note that there will be a negligible colour difference due to the loss of precision in green.
<br><br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| -
| 0x400-0x7FC
| -
| -
| Reserved
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| CursorImage
| 0x800-0xBFC
| R/W
| 0x00000000
| Cursor Image RAM Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| ClcdCrsrCtrl
| 0xC00
| R/W
| 0x00
| Cursor Control Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| ClcdCrsrConfig
| 0xC04
| R/W
| 0x0
| Cursor Configuration Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| ClcdCrsrPalette0
| 0xC08
| R/W
| 0x000000
| Cursor Palette Registers
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| ClcdCrsrPalette1
| 0xC0C
| R/W
| 0x000000
| Cursor Palette Registers
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| ClcdCrsrXY
| 0xC10
| R/W
| 0x00000000
| Cursor XY Position Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| ClcdCrsrClip
| 0xC14
| R/W
| 0x0000
| Cursor Clip Position Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| -
| 0xC18-0xC1C
| -
| -
| Reserved
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| ClcdCrsrIMSC
| 0xC20
| R/W
| 0x0
| Cursor Interrupt Mask Set/Clear Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| ClcdCrsrICR
| 0xC24
| WO
| 0x0
| Cursor Interrupt Clear Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| ClcdCrsrRIS
| 0xC28
| RO
| 0x0
| Cursor Raw Interrupt Status Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| ClcdCrsrMIS
| 0xC2C
| RO
| 0x0
| Cursor Masked Interrupt Status Register
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| -
| 0xC30-0xDFC
| -
| -
| Reserved
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| -
| 0xF00-0xF08
| -
| -
| Programmers Model for Test
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| -
| 0xF0C-0xFDC
| -
| -
| Reserved
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| CLCDPeriphID0
| 0xFE0
| RO
| 0x11
| Peripheral Identification Register 0
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| CLCDPeriphID1
| 0xFE4
| RO
| 0x11
| Peripheral Identification Register 1
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| CLCDPeriphID2
| 0xFE8
| RO
| 0x-4a
| Peripheral Identification Register 2
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| CLCDPeriphID3
| 0xFEC
| RO
| 0x00
| Peripheral Identification Register 3
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| CLCDPCellID0
| 0xFF0
| RO
| 0x0D
| PrimeCell Identification Register 0
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| CLCDPCellID1
| 0xFF4
| RO
| 0xF0
| PrimeCell Identification Register 1
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| CLCDPCellID2
| 0xFF8
| RO
| 0x05
| PrimeCell Identification Register 2
|}
<br>

{|border="1" cellspacing="0" cellpadding="5"
|-
! Name
! Base Offset
! Type
! Reset Value
! Description
|-
| CLCDPCellID3
| 0xFFC
| RO
| 0xB1
| PrimeCell Identification Register 3
|}
<br>