View source for 86:LCD Controller

[[Category:86:General Hardware Information|LCD Controller]]
The TI-86 has a memory-mapped STN liquid crystal display. The main portion of LCD controller is inside the [[86:ASIC|ASIC]], with row & column drivers & circuitry to produce the necessary voltages located on a daughterboard on which the LCD itself is also mounted.

== DMA ==
When the LCD is enabled, the ASIC needs to send pixels to it continuously. In order to allow the CPU to operate at the same time, the ASIC contains an internal buffer used to hold the pixels for the current row. This buffer is filled via DMA (direct memory access) that pauses the CPU once per row. This pause appears to be implemented internally by way of the Z80 signals /BUSREQ & /BUSACK, & as such, it is even able to occur in between the M cycles of a single instruction. No DMA is performed when the LCD is disabled.

The LCD always uses all 64 rows per physical frame. If the number of rows per logical frame is set lower than 64 via bits 1-2 of [[86:Ports:04|Port 04]], the subsequent logical frames are stacked vertically until the whole 64 rows are filled, with the last one being cut short if the rows per frame is set to 48. This stacking also makes the image darker, presumably because it increases the effective duty cycle.

The LCD controller always sends 160 pixels per row to the daughterboard, of which the first 80 & last 48 are visible on screen, for a total of 128 visible columns. However, DMA only reads as many bytes as necessary to contain the number of columns chosen via bits 3-4 of [[86:Ports:04|Port 04]]. Of the columns read via DMA, the first 80 are placed at the beginning of the buffer, & the remainder are placed at the end of the buffer. If this is fewer than the full 160 columns, the 4 columns immediately after the first 80 are copied from the last 4 of the previous row's DMA transfer. The remaining columns are copied starting from the beginning of the current row's DMA transfer.

== Interrupts ==
LCD interrupts occur twice per logical frame. They occur one row after one quarter & three quarters of the way down the frame, which is rows 17 & 49 (counting from 0) when set to 64 rows per frame. DMA occurs after the interrupt acknowledgement, which in particular is after the CPU reads the byte used to determine which offset to use for IM 2. The start of the interrupt service routine itself is then delayed until DMA finishes.

Warning: Toggling individual pixels every other interrupt may damage the LCD by causing a net charge to accumulate. Any given pixel's value should only be changed (at most) once every fourth interrupt. This is because the pixels of STN LCDs must be driven using AC waveforms to prevent damage due to charge buildup, & the calculator achieves this by alternating between 2 sets of voltages on consecutive frames.