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		<title>68k:Ports:600003 - Revision history</title>
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		<updated>2026-04-05T17:37:14Z</updated>
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	<entry>
		<id>https://wikiti.brandonw.net/index.php?title=68k:Ports:600003&amp;diff=4765&amp;oldid=prev</id>
		<title>Jib at 03:24, 5 June 2006</title>
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				<updated>2006-06-05T03:24:39Z</updated>
		
		<summary type="html">&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;[[Category:68k:Ports:By Address|600003]] [[Category:68k:Ports:By Name|Bus Wait States]]&lt;br /&gt;
&lt;br /&gt;
* Bit 6-4: Bus wait states (=7-n) for non-RAM accesses&lt;br /&gt;
* Bit 2-0: Bus wait states (=7-n) for RAM accesses&lt;br /&gt;
&lt;br /&gt;
The TI-89 hardware needs no wait states.&lt;/div&gt;</summary>
		<author><name>Jib</name></author>	</entry>

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