83Plus:Ports:08 - Revision history

Dr. D'nar: More information

2020-03-03T23:02:27Z

More information

Saibot84: contradiction with Interrupts section

2007-12-27T19:42:30Z

contradiction with Interrupts section

Dan Englender: /* Interrupts */ english

2006-03-28T23:36:52Z

‎Interrupts: english

Jim e: added to synopsis, oh and i did previous edits, got logged out.

2005-08-21T14:42:38Z

added to synopsis, oh and i did previous edits, got logged out.

70.117.202.191: More info

2005-08-21T13:02:45Z

More info

AndyJ: grammar slipups

2005-08-20T19:18:39Z

grammar slipups

Jim e: Added more info on interrupts

2005-08-20T07:19:28Z

Added more info on interrupts

Jim e: Added interrupt info

2005-07-23T01:21:38Z

Added interrupt info

FloppusMaximus at 05:18, 30 March 2005

2005-03-30T05:18:08Z

FloppusMaximus at 02:23, 29 March 2005

2005-03-29T02:23:42Z

@@ Line 9: / Line 9: @@
 === Read Values ===
 * Bit 0: 1 if link assist will generate an interrupt when a byte is received. (Link assist must be enabled)
-* Bit 1: 1 if link assist will generate an interrupt when a byte can be sent. (Link assist must be enabled)
+* Bit 1: 1 if link assist will generate an interrupt when a byte has been sent. (Link assist must be enabled)
 * Bit 2: 1 if link assist will generate an interrupt when an error has occurred. (Link assist must be enabled)
 * Bit 7: 1 if the link assist is disabled.
 === Write Values ===
 * Bit 0: Set to generate an interrupt when link assist receives a byte. (Link assist must be enabled)
-* Bit 1: Set to generate an interrupt when link assist is able to send byte. (Link assist must be enabled)
+* Bit 1: Set to generate an interrupt when link assist has finished sending a byte. (Link assist must be enabled)
 * Bit 2: Set to generate an interrupt when an error occurs. (Link assist must be enabled)
 * Bit 7: 1 to disable the link assist.

@@ Line 8: / Line 8: @@
 === Read Values ===
-* Bit 1: 1 if link assist will generate an interrupt when a byte is received. (Link assist must be enabled)
+* Bit 0: 1 if link assist will generate an interrupt when a byte is received. (Link assist must be enabled)
-* Bit 2: 1 if link assist will generate an interrupt when a byte can be sent. (Link assist must be enabled)
+* Bit 1: 1 if link assist will generate an interrupt when a byte can be sent. (Link assist must be enabled)
-* Bit 3: 1 if link assist will generate an interrupt when an error has occurred. (Link assist must be enabled)
+* Bit 2: 1 if link assist will generate an interrupt when an error has occurred. (Link assist must be enabled)
 * Bit 7: 1 if the link assist is disabled.
 === Write Values ===
-* Bit 1: Set to generate an interrupt when link assist receives a byte. (Link assist must be enabled)
+* Bit 0: Set to generate an interrupt when link assist receives a byte. (Link assist must be enabled)
-* Bit 2: Set to generate an interrupt when link assist is able to send byte. (Link assist must be enabled)
+* Bit 1: Set to generate an interrupt when link assist is able to send byte. (Link assist must be enabled)
-* Bit 3: Set to generate an interrupt when an error occurs. (Link assist must be enabled)
+* Bit 2: Set to generate an interrupt when an error occurs. (Link assist must be enabled)
 * Bit 7: 1 to disable the link assist.

@@ Line 41: / Line 41: @@
-The biggest benefit from the link assist interrupts is that no time must wasted waiting, it could take millisecond to send or receive a byte. With interrupts that time can be put to more useful code. I don't believe that you should have both the send and receive interrupts enabled at the same. But really communication would dictate who is sending and receiving. Remember that TI-OS does not seem to handle these interrupts, disable them when your through.
+The biggest benefit from the link assist interrupts is that no time must wasted waiting, it could take millisecond to send or receive a byte. With interrupts that time can be put to more useful code. I don't believe that you should have both the send and receive interrupts enabled at the same. But really communication would dictate who is sending and receiving. Remember that TI-OS does not seem to handle these interrupts, disable them when you're through.
-−
-−
 == Credits and Contributions ==
 * '''Michael Vincent:''' Original documentation of the link assist
 * '''James Montelongo:''' Interrupt information

@@ Line 5: / Line 5: @@
 '''Function:''' Link Assist Enable
-This port controls whether the hardware link assist is enabled.
+This port controls whether the hardware link assist is enabled. It also controls what interrupts the link assist will generate.
 === Read Values ===

@@ Line 10: / Line 10: @@
 * Bit 1: 1 if link assist will generate an interrupt when a byte is received. (Link assist must be enabled)
 * Bit 2: 1 if link assist will generate an interrupt when a byte can be sent. (Link assist must be enabled)
 * Bit 7: 1 if the link assist is disabled.
@@ Line 15: / Line 16: @@
 * Bit 1: Set to generate an interrupt when link assist receives a byte. (Link assist must be enabled)
 * Bit 2: Set to generate an interrupt when link assist is able to send byte. (Link assist must be enabled)
 * Bit 7: 1 to disable the link assist.
@@ Line 22: / Line 24: @@
 Programs which directly control the link port should disable the hardware assist.
 ===Interrupts===
-Link Assist hardware can generate an interrupt when a byte is received or when a byte can be sent.
+Link Assist hardware can generate an interrupt when a byte is received, when a byte can be sent or when an error in transmission occurs.
@@ Line 31: / Line 35: @@
-To enable an interrupt when a byte can be sent write 2 to port 08. When the the link assist is not busy it will generate an interrupt so you can send data. When this interrupt is generated bit 1 of port 9 is set. You acknowledge this interrupt by writing to port 0D.
+To enable an interrupt when a byte can be sent write 2 to port 08. When the the link assist is not busy it will generate an interrupt so you can send data. Bit 1 of port 9 is set when this interrupt generates. You acknowledge this interrupt by writing to port 0D.
-The biggest benefit from the link assist interrupts is that no time must wasted waiting, it could take millisecond to send or receive a byte. With interrupts that time can be put to more useful code. I don't believe that you should have both of these interrupts enabled at the same. But really communication would dictate who is sending and receiving. Remember that TI-OS does not seem to handle these interrupts, disable them when your through.
+The biggest benefit from the link assist interrupts is that no time must wasted waiting, it could take millisecond to send or receive a byte. With interrupts that time can be put to more useful code. I don't believe that you should have both the send and receive interrupts enabled at the same. But really communication would dictate who is sending and receiving. Remember that TI-OS does not seem to handle these interrupts, disable them when your through.

@@ Line 1: / Line 1: @@
-[[Category:83Plus:Ports:By_Address|08 - Link Assist Enable]]
+[[Category:83Plus:Ports:By_Address|08 - Link Assist Enable]] [[Category:83Plus:Ports:By_Name|Link Assist Enable]]
 [[Category:83Plus:Ports:By_Name|Link Assist Enable]]
 == Synopsis ==
 '''Port Number:''' 08h

@@ Line 1: / Line 1: @@
-'''Note:''' Do not take the information on this template page as actual documentation!
+[[Category:83Plus:Ports:By_Address|08 - Link Assist Enable]]
+[[Category:83Plus:Ports:By_Name|Link Assist Enable]]
-The Ports are named by their number, in hexadecimal. An example is [[83Plus:Ports:00]].
-−
-You also must put a variation on the following code into your page to have it categorized:
- NaodW29-nowiki4ba326a46ee8fcd600000001
-−
-----
-−
 == Synopsis ==
-'''Port Number:''' 06h
+'''Port Number:''' 08h
-'''Function:''' Flash Memory Paging
+'''Function:''' Link Assist Enable
-This port controls what page is swapped into the 4000h to 7FFFh range. ('''DO NOT''' take this template page as real documentation on port 6!)
+This port controls whether the hardware link assist is enabled.
 === Read Values ===
-* [00h - FFh]: The current port mapped to the memory range 4000h through 7FFFh.
+* Bit 7: 1 if the link assist is disabled.
 === Write Values ===
-* [00h - FFh]: The new page to swap in to the memory range 4000h through 7FFFh
+* Bit 7: 1 to disable the link assist.
-−
-''Note: if you would have bitwise flags for your port, label them "bit X".''
 == Comments ==
-The behavior of this port changes in different memory map modes.
+This port only exists on the 83+ SE and the 84+.
-== Example ==
+Programs which directly control the link port should disable the hardware assist.
- NaodW29-nowiki4ba326a46ee8fcd600000002
 == Credits and Contributions ==
-* '''/dev/urandom:''' Because of your randomness, this project is possible.
+* '''Michael Vincent:''' Original documentation of the link assist