83Plus:Ports:29 - Revision history

Calc84maniac at 06:49, 19 February 2013

2013-02-19T06:49:43Z

2011-10-28T03:49:05Z

2011-10-28T03:09:30Z

2011-07-05T22:43:53Z

2006-03-14T14:05:14Z

added warning about lcd not updating.

2006-03-14T14:00:00Z

added 2e info

2005-08-22T09:06:53Z

Added bit 1 info

2005-08-21T20:30:02Z

Added info on effect

2005-08-08T21:48:46Z

‎Synopsis: ... effect is somewhat more general

2005-08-08T05:57:17Z

Renamed to better fit it

← Older revision		Revision as of 06:49, 19 February 2013
Line 20:		Line 20:

	The effect of this port is only seen if the contents of [[83Plus:Ports:20\|port 20h]] equals 00.		The effect of this port is only seen if the contents of [[83Plus:Ports:20\|port 20h]] equals 00.
		+
		+	As noted above, a delay less than 3 cycles causes LCD outputs to fail. However, it seems that LCD inputs (from any port) will work with a delay of 1 or more. With a delay of 0, both inputs and outputs seem to fail. Is this all a hardware glitch? Who knows.

@@ Line 1: / Line 1: @@
 [[Category:83Plus:Ports:By Address|29 - LCD Delay (6 MHz)]] [[Category:83Plus:Ports:By Name|LCD Delay (6 MHz)]]
-{{SE-Only Port|09}}
+{{SE-Only Port|01}}
 == Synopsis ==

@@ Line 1: / Line 1: @@
 [[Category:83Plus:Ports:By Address|29 - LCD Delay (6 MHz)]] [[Category:83Plus:Ports:By Name|LCD Delay (6 MHz)]]
-{{SE-Only Port|01}}
+{{SE-Only Port|09}}
 == Synopsis ==

@@ Line 12: / Line 12: @@
 * Bit 0 enables the effects of the flash delay controlled by port 2E.
 * Bit 1 enables the effects of the ram delay controlled by port 2E.
-* Bits 2-7 control the amount of delay added at specified instructions. To calculate the number of clock cycles added, divide the contents of port 29 by 4 and round off. '''NOTE:''' The contents of this port should NOT be less than 0Ch or the LCD will no longer update.
+* Bits 2-7 control the amount of delay added at specified instructions. To calculate the number of clock cycles added, divide the contents of port 29 by 4 and round off. '''NOTE:''' The contents of this port should NOT be less than 0Ch or the LCD driver will no longer respond.
 == Comments ==

@@ Line 12: / Line 12: @@
 * Bit 0 enables the effects of the flash delay controlled by port 2E.
 * Bit 1 enables the effects of the ram delay controlled by port 2E.
-* Bits 2-7 control the amount of delay added at specified instructions. To calculate the number of clock cycles added, divide the contents of port 29 by 4 and round off.
+* Bits 2-7 control the amount of delay added at specified instructions. To calculate the number of clock cycles added, divide the contents of port 29 by 4 and round off. '''NOTE:''' The contents of this port should NOT be less than 0Ch or the LCD will no longer update.
 == Comments ==

@@ Line 11: / Line 11: @@
 === Usage ===
-Bits 0 and 1 are unknown, but don't seem to directly remove the needed delay. On the 83+SE these are reset, on the 84+(SE) these are set.
+When Bit 1 is set the effects of speed adjustment port 2E can be seen.
 Bits 2-7 control the amount of delay added at specified instructions. To calculate the number of clock cycles added, divide the contents of port 29 by 4 and round off.
@@ Line 18: / Line 18: @@
 This port is not available on the normal TI-83+. On the normal TI-83+ this port is a shadow of [[83Plus:Ports:01|Port 01h]].
-Bits 0&1 seem to tie to port 2E, they affect the cpu speed reduction the port 2e contorls. Though their exact purpose is not known.
+Bits 0&1 are reset on the 83+SE and set on the 84+(se).
 The effect of this port is only seen if the contents of [[83Plus:Ports:20|port 20h]] equals 00.

← Older revision		Revision as of 20:30, 21 August 2005
Line 19:		Line 19:

	Bits 0&1 seem to tie to port 2E, they affect the cpu speed reduction the port 2e contorls. Though their exact purpose is not known.		Bits 0&1 seem to tie to port 2E, they affect the cpu speed reduction the port 2e contorls. Though their exact purpose is not known.
		+
		+	The effect of this port is only seen if the contents of [[83Plus:Ports:20\|port 20h]] equals 00.

@@ Line 7: / Line 7: @@
 '''Function:''' LCD Delay (6 MHz)
-This port removes the amount of delay needed between accesses to the lcd driver by adding tstates to the following instructions:
+This port removes the amount of delay needed between accesses to the LCD driver by adding a delay to any instruction which reads from or writes to ports [[83Plus:Ports:10|10]] or [[83Plus:Ports:11|11]], as well as the mirror ports 12 and 13.
-* out (010h),a
-* in a,(011h)
-* out (011h),a
-−
 === Usage ===
-Bits 0&1 are unknown, but don't seem to directly remove the needed delay. On the 83+SE these are reset, on the 84+(SE) these are set.
+Bits 0 and 1 are unknown, but don't seem to directly remove the needed delay. On the 83+SE these are reset, on the 84+(SE) these are set.
-−
-Bits 2-7 control the amount of delay added at specified instructions. To calculate the tstates added divide the contents of port 29 by 4 and round off.
 == Comments ==