83Plus:Ports:2F - Revision history

Dr. D'nar: More information

2020-03-03T23:30:19Z

More information

KermMartian at 05:51, 17 March 2013

2013-03-17T05:51:47Z

Thepenguin77 at 03:50, 28 October 2011

2011-10-28T03:50:19Z

Thepenguin77 at 03:11, 28 October 2011

2011-10-28T03:11:21Z

70.117.202.191: Rewrote with more accurate data, someone may want to rephrase a few things.

2005-10-05T12:27:12Z

Rewrote with more accurate data, someone may want to rephrase a few things.

Jim e: Spell check by google(i warned you bout my typos andy)

2005-08-23T14:05:55Z

Spell check by google(i warned you bout my typos andy)

AndyJ: /* Write Values */ contorl --> control, x3 (aka typo squad)

2005-08-23T13:53:54Z

‎Write Values: contorl --> control, x3 (aka typo squad)

Jim e: Minor mistake

2005-08-23T13:47:56Z

Minor mistake

Jim e: Remaining bits plus more accurate timing

2005-08-23T13:03:59Z

Remaining bits plus more accurate timing

Jim e: Foregot SE only

2005-08-08T18:31:58Z

Foregot SE only

@@ Line 1: / Line 1: @@
-[[Category:83Plus:Ports:By Address|2F - LCD Wait Delay]]
+[[Category:83Plus:Ports:By Address|2F - LCD Wait Delay/Crystal Timer Adjust]]
-[[Category:83Plus:Ports:By Name|LCD Wait Delay]]
+[[Category:83Plus:Ports:By Name|LCD Wait Delay/Crystal Timer Adjust]]
 {{SE-Only Port|07}}
@@ Line 6: / Line 6: @@
 '''Port Number:''' 2Fh
-'''Function:''' LCD Wait Delay
+'''Function:''' LCD Wait Delay/Crystal Timer Adjust
-After every write to the LCD bit 1 of [[83Plus:Ports:02|port 2]] resets for a certain amount of time based on the current cpu speed and if the calculator is in hi speed mode. This port is used to adjust the LCD delay to be the same amount of wallclock time no matter what speed setting the CPU is in, as if it was operating in 6MHz mode. It is believed that the three bit groupings below define the amount to divide the system clock by.
+After every write to the LCD bit 1 of [[83Plus:Ports:02|port 2]] resets for a certain amount of time based on the current cpu speed and if the calculator is in hi speed mode. This port is used to adjust the LCD delay to be the same amount of wallclock time no matter what speed setting the CPU is in, as if it was operating in 6MHz mode. The three bit groupings below define the amount to divide the system clock by. This is nominally in increments of 64 T-states, so I'm not sure where the -16 offset comes from.

← Older revision		Revision as of 05:51, 17 March 2013
Line 8:		Line 8:
	'''Function:''' LCD Wait Delay		'''Function:''' LCD Wait Delay

−	After every write to the LCD bit 1 of [[83Plus:Ports:02\|port 2]] resets for a certain amount of time based on the current cpu speed and if the calculator is in hi speed mode. This port ~~controls that~~ amount time.	+	After every write to the LCD bit 1 of [[83Plus:Ports:02\|port 2]] resets for a certain amount of time based on the current cpu speed and if the calculator is in hi speed mode. This port is used to adjust the LCD delay to be the same amount of wallclock time no matter what speed setting the CPU is in, as if it was operating in 6MHz mode. It is believed that the three bit groupings below define the amount to divide the system clock by.

@@ Line 1: / Line 1: @@
 [[Category:83Plus:Ports:By Address|2F - LCD Wait Delay]]
 [[Category:83Plus:Ports:By Name|LCD Wait Delay]]
-{{SE-Only Port|0F}}
+{{SE-Only Port|07}}
 == Synopsis ==

@@ Line 1: / Line 1: @@
 [[Category:83Plus:Ports:By Address|2F - LCD Wait Delay]]
 [[Category:83Plus:Ports:By Name|LCD Wait Delay]]
-{{SE-Only Port|07}}
+{{SE-Only Port|0F}}
 == Synopsis ==

@@ Line 8: / Line 8: @@
 '''Function:''' LCD Wait Delay
-After every write to the LCD bit 1 of [[83Plus:Ports:02|port 2]] resets for a certain amount of time. This port controls that amount time.
+After every write to the LCD bit 1 of [[83Plus:Ports:02|port 2]] resets for a certain amount of time based on the current cpu speed and if the calculator is in hi speed mode. This port controls that amount time.
@@ Line 16: / Line 16: @@
 === Write Values ===
-* Bits 0-1 control the amount of time when port 20 contains 1. The following values tell the amount of time.
+* Bits 0-1 control the amount of tstates to wait when port 20 contains 1. The following values tell the number of tstates.
-** 00 = ~3.2 microseconds
+** 00 = 048 tstates
-** 01 = ~7.4 microseconds
+** 01 = 112 tstates
-** 10 = ~11.7 microseconds
+** 10 = 176 tstates
-** 11 = ~16.0 microseconds
+** 11 = 240 tstates
-* Bits 2-4 control the amount of time when port 20 contains 2. The following values tell the amount of time.
+* Bits 2-4 control the amount of tstates to wait when port 20 contains 2. The following values tell the number of tstates.
-** 000 = ~3.2 microseconds
+** 000 = 048 tstates
-** 001 = ~7.4 microseconds
+** 001 = 112 tstates
-** 010 = ~11.7 microseconds
+** 010 = 176 tstates
-** 011 = ~16.0 microseconds
+** 011 = 240 tstates
-** 100 = ~20.2 microseconds
+** 100 = 304 tstates
-** 101 = ~24.5 microseconds
+** 101 = 368 tstates
-** 110 = ~28.8 microseconds
+** 110 = 432 tstates
-** 111 = ~33.0 microseconds
+** 111 = 496 tstates
-* Bits 5-7 control the amount of time when port 20 contains 3. The following values tell the amount of time.
+* Bits 5-7 control the amount of tstates to wait when port 20 contains 3. The following values tell the number of tstates.
-** 000 = ~3.2 microseconds
+** 000 = 048 tstates
-** 001 = ~7.4 microseconds
+** 001 = 112 tstates
-** 010 = ~11.7 microseconds
+** 010 = 176 tstates
-** 011 = ~16.0 microseconds
+** 011 = 240 tstates
-** 100 = ~20.2 microseconds
+** 100 = 304 tstates
-** 101 = ~24.5 microseconds
+** 101 = 368 tstates
-** 110 = ~28.8 microseconds
+** 110 = 432 tstates
-** 111 = ~33.0 microseconds
+** 111 = 496 tstates
 == Comments ==

@@ Line 12: / Line 12: @@
 === Read Values ===
-* This port reads the last vaule written to it.
+* This port reads the last value written to it.
@@ Line 46: / Line 46: @@
 This value really shouldn't be changed. TI-OS depends on this being set high enough to function for the LCD delay.
-Also the 83+SE has this port set to 4A as defualt, the 84+(SE) has this port set to 4B as defualt.
+Also the 83+SE has this port set to 4A as default, the 84+(SE) has this port set to 4B as default.
 == Credits and Contributions ==
 * '''James Montelongo'''