84PCE:LCD Controller - Revision history

Calc84maniac: Document internal RAM read behavior

2024-06-13T20:59:29Z

Document internal RAM read behavior

Calc84maniac: /* 3A: Interface Pixel Format */ Update bitfield ranges

2024-06-10T23:20:24Z

‎3A: Interface Pixel Format: Update bitfield ranges

Calc84maniac: Document behavior of fixed scroll areas of 320 and larger

2024-06-08T00:37:23Z

Document behavior of fixed scroll areas of 320 and larger

Calc84maniac: Add information about out-of-range RAM accesses

2024-06-07T17:23:52Z

Add information about out-of-range RAM accesses

Calc84maniac: Update descriptions of DE/HV modes throughout

2024-05-30T19:59:06Z

Update descriptions of DE/HV modes throughout

Calc84maniac: /* RGB Interface */ Improve timing documentation and add HV mode descriptions

2024-05-30T19:23:00Z

‎RGB Interface: Improve timing documentation and add HV mode descriptions

Calc84maniac: Add information about clock rate variance

2024-05-30T17:14:06Z

Add information about clock rate variance

Calc84maniac: /* B0: RAM Control */ Document reserved display mode

2024-05-22T04:21:44Z

‎B0: RAM Control: Document reserved display mode

Calc84maniac: /* 33: Vertical Scrolling Definition */ Fix typos

2024-05-21T19:45:04Z

‎33: Vertical Scrolling Definition: Fix typos

Calc84maniac: Add Gate Control and other misc. commands

2024-03-10T05:55:40Z

Add Gate Control and other misc. commands

@@ Line 40: / Line 40: @@
 In HV mode, the data enable signal is ignored and the porches configured in [[#B1: RGB Interface Control|RGB Interface Control]] are used to determine when pixel data is accepted. To align the pixel data correctly, the RGB interface's configured VSYNC and HSYNC back porches should equal the sum of the Primecell's corresponding Sync Width and Back Porch, and the active video area should be 240x320 pixels. When pixel data is misaligned, pixel clocks outside of the Primecell's active video will write all-zero (black) pixels to display RAM.
-To prevent scan errors, the Primecell must be configured with at least 257 pixel clocks per line (including porches), which allows enough time for the RAM reads starting 17 pixel clocks into each line. The datasheet recommends at least 22 pixel clocks of total porch, for at least 262 pixel clocks per line total.
+To prevent scan errors, the Primecell must be configured with at least 257 pixel clocks per line (including porches), which allows enough time for the RAM reads starting 17 pixel clocks into each line (see [[#Internal Reads|Internal Reads]]). The datasheet recommends at least 22 pixel clocks of total porch, for at least 262 pixel clocks per line total.
 In DE mode, active video begins one line after the Primecell first asserts the data enable signal (meaning it begins at the Primecell's second line of active video), so there should be at least 321 lines combined in the Primecell's active video and front porch. In HV mode, the RGB interface VSYNC back porch is configured in [[#B1: RGB Interface Control|RGB Interface Control]], so the Primecell's total number of lines (including porches) should be at least the configured back porch plus 320. If the number of lines is too small, the frame synchronization pulse will be ignored until all 320 lines of active video have been scanned, causing the refresh rate to be halved or more.
@@ Line 97: / Line 97: @@
 RGB666 format (3 bytes per pixel): 1<span style="color: #00f">BBBBBB</span>XX 1<span style="color: #0c0">GGGGGG</span>XX 1<span style="color: #f00">RRRRRR</span>XX
 = Command List =
@@ Line 735: / Line 781: @@
 |N/A
 |RTNB: Frame rate control for Idle Mode. Affects the duration of each line. See the formula above for how this value is used.
-Should be greater than 0, or else the number of pixel clocks per line will be too small, as the limits are described in [[#RGB Interface|RGB Interface]].
+Should be greater than 0, or else the number of pixel clocks per line will be too small for the [[#Internal Reads|Internal Reads]].
 |-
 |7:5
@@ Line 756: / Line 802: @@
 |N/A
 |RTNC: Frame rate control for Partial Mode. Affects the duration of each line. See the formula above for how this value is used.
-Should be greater than 0, or else the number of pixel clocks per line will be too small, as the limits are described in [[#RGB Interface|RGB Interface]].
+Should be greater than 0, or else the number of pixel clocks per line will be too small for the [[#Internal Reads|Internal Reads]].
 |-
 |7:5
@@ Line 995: / Line 1,041: @@
 |0Fh
 |RTNA: Frame rate control for Normal Mode. Affects the duration of each line. See the formula above for how this value is used.
-Should be greater than 0, or else the number of pixel clocks per line will be too small, as the limits are described in [[#RGB Interface|RGB Interface]].
+Should be greater than 0, or else the number of pixel clocks per line will be too small for the [[#Internal Reads|Internal Reads]].
 |-
 |7:5

@@ Line 433: / Line 433: @@
 |<u>Description</u>
 |-
-|3:0
+|2:0
 |06h
 |06h
@@ Line 441: / Line 441: @@
 * 06h: 18 bits per pixel (RGB666)
 |-
-|7:4
+|6:4
 |06h
 |06h

@@ Line 303: / Line 303: @@
 |0000h
 |N/A
-|TFA: Top Fixed Area. Should be between 0 and 320-BFA, inclusive.
+|TFA: Top Fixed Area. Should be between 0 and 320-BFA, inclusive. If 320 or greater, fills the whole screen.
 |}
@@ Line 329: / Line 329: @@
 |0000h
 |N/A
-|BFA: Bottom Fixed Area. Should be between 0 and 320-TFA, inclusive.
+|BFA: Bottom Fixed Area. Should be between 0 and 320-TFA, inclusive. If 320 or greater, this area is disabled.
 |}
@@ Line 400: / Line 400: @@
 If the ML bit is set in [[#36: Memory Data Access Control|Memory Data Access Control]], the line address is interpreted from right to left and VSP is the line to display on the right-hand side, so while VSP=TFA still means no scrolling, increasing the value scrolls the area to the right instead.
-The scrolling is designed such that only the lines within the scroll area are rotated; when line 320-BFA is reached in frame memory, the line address returns to TFA. Strictly speaking, the first time in a frame that the line address is ''at least'' 320-BFA, (320-BFA)-TFA is subtracted from the line address. This can be useful knowledge when using the scroll mode for unintended behavior like showing the same lines in multiple parts of the screen. However, if the line address ever remains between 320 and 511 after scroll area wrapping is applied, it attempts to access invalid display RAM addresses and displays garbage, so that should be avoided.
+The scrolling is designed such that only the lines within the scroll area are rotated; when line 320-BFA is reached in frame memory, the line address returns to TFA. Strictly speaking, the first time in a frame that the line address is ''greater than'' 319-BFA, (320-BFA)-TFA is subtracted from the line address. This can be useful knowledge when using the scroll mode for unintended behavior like showing the same lines in multiple parts of the screen. Also, if BFA is 320 or larger, the scroll area is located between [TFA, 320) and no wrapping occurs because 319-BFA is treated as a large positive number. If the line address ever remains between 320 and 511 after scroll area wrapping is applied, it attempts to access invalid display RAM addresses and displays garbage, so that should be avoided.
 '''Parameter word 1:'''

@@ Line 69: / Line 69: @@
 Before accessing RAM, a rectangular window should be configured using the [[#2A: Column Address Set|Column Address Set]] and [[#2B: Row Address Set|Row Address Set]] commands. Data is accessed using a Frame Memory Pointer (unique to each interface) which starts at a corner of the configured window and moves in the major (X) direction configured by the [[#36: Memory Data Access Control|Memory Data Access Control]] command. Once the opposite edge of the window is reached, it wraps around and moves the pointer in the minor (Y) direction. Once the opposite ''corner'' of the window has been reached, it either wraps around to the beginning or disallows writes until the Frame Memory Pointer is reset, depending on the WEMODE bits in [[#B0: RAM Control|RAM Control]].
 TI configures a full-screen row-major window by default (starting in the upper-left corner of the screen, moving left to right across a row, and proceeding through each row from top to bottom). This causes the diagonal screen tearing effect commonly seen on the CE, because each line (column) is only partially updated when scanned to the display.
@@ Line 398: / Line 400: @@
 If the ML bit is set in [[#36: Memory Data Access Control|Memory Data Access Control]], the line address is interpreted from right to left and VSP is the line to display on the right-hand side, so while VSP=TFA still means no scrolling, increasing the value scrolls the area to the right instead.
-The scrolling is designed such that only the lines within the scroll area are rotated; when line 320-BFA is reached in frame memory, the line address returns to TFA. Strictly speaking, the first time in a frame that the line address is ''at least'' 320-BFA, (320-BFA)-TFA is subtracted from the line address. This can be useful knowledge when using the scroll mode for unintended behavior like showing the same lines in multiple parts of the screen.
+The scrolling is designed such that only the lines within the scroll area are rotated; when line 320-BFA is reached in frame memory, the line address returns to TFA. Strictly speaking, the first time in a frame that the line address is ''at least'' 320-BFA, (320-BFA)-TFA is subtracted from the line address. This can be useful knowledge when using the scroll mode for unintended behavior like showing the same lines in multiple parts of the screen. However, if the line address ever remains between 320 and 511 after scroll area wrapping is applied, it attempts to access invalid display RAM addresses and displays garbage, so that should be avoided.
 '''Parameter word 1:'''

@@ Line 48: / Line 48: @@
 == MCU Interface ==
-In this mode, all scan timings are internal. Signals from the RGB interface are ignored, aside from display RAM writes if enabled. Scan timings are determined by [[#B3: Frame Rate Control 1|Frame Rate Control 1]], [[#C6: Frame Rate Control 2|Frame Rate Control 2]], and [[#B2: Porch Setting|Porch Setting]].
+In this mode, all scan timings are internal. Signals from the RGB interface are ignored, aside from using the pixel clock, RGB pixel data, and data enable signals for display RAM writes if enabled in [[#B0: RAM Control|RAM Control]].
 == VSYNC Interface ==
-In this mode, all scan timings are internal ''except'' for the frame synchronization pulse. Other signals from the RGB interface are ignored, aside from display RAM writes if enabled.
+In this mode, all scan timings are internal ''except'' for the frame synchronization pulse. Other signals from the RGB interface are ignored, aside from using the pixel clock, RGB pixel data, and data enable signals for display RAM writes if enabled in [[#B0: RAM Control|RAM Control]].
 This mode allows the frame rate alone to be controlled by the RGB interface, while allowing much more flexibility with the timing of the line configuration, pixel clock, and RAM writes.
 Note that if the MCU interface timings are not configured to complete a frame faster than the RGB interface, some frame synchronization pulses will be ignored and the framerate will be effectively halved or more. Thus, MCU interface timings should be configured to account for LCD controllers with slower internal clock rate; see [[#C6: Frame Rate Control 2|Frame Rate Control 2]] for information on clock rate variance.
 = RAM access =
@@ Line 560: / Line 566: @@
 * 00h: MCU interface according to datasheet, seems to act like 02h.
 * 01h: MCU interface according to datasheet, seems to act like 03h.
-* 02h: RGB DE mode. Respects the Data Enable signal for accepting RGB pixel data. This mode should generally be used on the CE.
+* 02h: RGB DE mode. Respects the Data Enable signal for accepting RGB pixel data and starting active video. This mode should generally be used on the CE.
-* 03h: RGB HV mode. Accepts RGB pixel data during Horizontal/Vertical active video periods.
+* 03h: RGB HV mode. Accepts RGB pixel data during active video periods, determined by the HSYNC and VSYNC back porch settings.
 |-
 |7
@@ Line 581: / Line 587: @@
 |05h
 |VBP: RGB interface VSYNC back porch. Number of lines, including frame synchronization, to wait before active video.
-Seems to be ignored in RGB DE mode, instead waiting for the first line that the Data Enable signal is set.
+Ignored in RGB DE mode, instead waiting for the first line that the Data Enable signal is set if direct RGB mode is enabled, or the line after otherwise.
 In RGB HV mode, should be set to VSW+VBP (actual) in the Primecell's LCDTiming1 register.
 |}
@@ Line 596: / Line 602: @@
 |14h
 |HBP: RGB interface HSYNC back porch. Number of pixels, including line synchronization, to wait before active video.
-Seems to be ignored in RGB DE mode, instead waiting for the first pixel that the Data Enable signal is set.
+Ignored in RGB DE mode, instead waiting for the first pixel that the Data Enable signal is set.
 In RGB HV mode, should be set to HSW+HBP (actual) in the Primecell's LCDTiming0 register.
 |}
@@ Line 727: / Line 733: @@
 |N/A
 |RTNB: Frame rate control for Idle Mode. Affects the duration of each line. See the formula above for how this value is used.
 |-
 |7:5
@@ Line 747: / Line 754: @@
 |N/A
 |RTNC: Frame rate control for Partial Mode. Affects the duration of each line. See the formula above for how this value is used.
 |-
 |7:5
@@ Line 985: / Line 993: @@
 |0Fh
 |RTNA: Frame rate control for Normal Mode. Affects the duration of each line. See the formula above for how this value is used.
 |-
 |7:5

@@ Line 32: / Line 32: @@
 * Pixel clock (CLCP)
 * RGB pixel data (CLD)
-* Data enable (CLAC)
+* Data enable (CLAC), only if DE mode is enabled in [[#B1: RGB Interface Control|RGB Interface Control]].
-This is TI's default setting, and causes the scan timing to be completely controlled by the Primecell.
+RGB Interface with DE mode is TI's default setting, and causes the scan timing to be completely controlled by the Primecell.
-To prevent scan errors, the Primecell must be configured with at least 240 pixel clocks per line and at least 320 lines per frame, plus the back porch values configured in [[#B1: RGB Interface Control|RGB Interface Control]]. Note that these pixel clocks and lines are not required to be during active video of the Primecell, as it drives the pixel clock and line sync pulses even during porches.
+In DE mode, active video on the Primecell will drive the data enable and RGB pixel data signals, which are accepted by the RGB interface and written to display RAM, if enabled in [[#B0: RAM Control|RAM Control]].
-Active video on the Primecell will drive the data enable and RGB pixel data signals, which are accepted by the RGB interface and written to display RAM, if enabled.
+In HV mode, the data enable signal is ignored and the porches configured in [[#B1: RGB Interface Control|RGB Interface Control]] are used to determine when pixel data is accepted. To align the pixel data correctly, the RGB interface's configured VSYNC and HSYNC back porches should equal the sum of the Primecell's corresponding Sync Width and Back Porch, and the active video area should be 240x320 pixels. When pixel data is misaligned, pixel clocks outside of the Primecell's active video will write all-zero (black) pixels to display RAM.
-The RGB interface may also be configured with the WO bit of [[#B1: RGB Interface Control|RGB Interface Control]] to bypass display RAM entirely and output the RGB pixel data signals directly to the display. Of course, this requires precisely a 240x320 active video configuration on the Primecell (in CE memory, represented in column-major order).
+To prevent scan errors, the Primecell must be configured with at least 257 pixel clocks per line (including porches), which allows enough time for the RAM reads starting 17 pixel clocks into each line. The datasheet recommends at least 22 pixel clocks of total porch, for at least 262 pixel clocks per line total.
 == MCU Interface ==

@@ Line 52: / Line 52: @@
 This mode allows the frame rate alone to be controlled by the RGB interface, while allowing much more flexibility with the timing of the line configuration, pixel clock, and RAM writes.
-Note that if the MCU interface timings are not configured to complete a frame faster than the RGB interface, some frame synchronization pulses will be ignored and the framerate will be effectively halved or more.
+Note that if the MCU interface timings are not configured to complete a frame faster than the RGB interface, some frame synchronization pulses will be ignored and the framerate will be effectively halved or more. Thus, MCU interface timings should be configured to account for LCD controllers with slower internal clock rate; see [[#C6: Frame Rate Control 2|Frame Rate Control 2]] for information on clock rate variance.
 = RAM access =
@@ Line 683: / Line 683: @@
 The refresh rate can be calculated as 10MHz/divisor/(number of lines)/(250+RTN*16).
 The number of lines depends on the [[#B2: Porch Setting|Porch Setting]], and is equal to (BP+320+FP) in MCU Interface mode and a minimum of (BP+320) in VSYNC Interface mode.
@@ Line 959: / Line 961: @@
 The refresh rate can be calculated as 10MHz/divisor/(number of lines)/(250+RTNA*16).
 The divisor is specified in [[#B3: Frame Rate Control 1|Frame Rate Control 1]].

@@ Line 464: / Line 464: @@
 * 01h: RGB Interface
 * 02h: VSYNC Interface
-* 03h: Reserved
+* 03h: Reserved. Acts like 00h.
 |-
 |4

@@ Line 275: / Line 275: @@
 Changes to the scroll area only take effect at the next frame start.
-The TFA lines on the left side of the screen are displayed normally, as well as the TBA lines on the right side of the screen. The lines in the middle range [TFA, 320-BFA) participate in horizontal scrolling.
+The TFA lines on the left side of the screen are displayed normally, as well as the BFA lines on the right side of the screen. The lines in the middle range [TFA, 320-BFA) participate in horizontal scrolling.
-If the ML bit is set in [[#36: Memory Data Access Control|Memory Data Access Control]], the scrolling range is interpreted from right to left, making it [TFA, 320-BFA) under normal line numbering.
+If the ML bit is set in [[#36: Memory Data Access Control|Memory Data Access Control]], the scrolling range is interpreted from right to left, making it [BFA, 320-TFA) under normal line numbering.
 The datasheet specifies that VSA should hold the number of lines in the scrolling range such that TFA+VSA+BFA=320, but VSA seems to have no effect in practice.

@@ Line 1,023: / Line 1,023: @@
 |02h (6.8V)
 |AVDD: AVDD setting.
 |}
@@ Line 1,571: / Line 1,587: @@
 |N/A
 |DGM_LUT_Bn: The output mapping when the color component value is equal to n. As mentioned above, when n is odd, the mapping for n-1 is used instead.
 |}