84PCE:Ports:1005 - Revision history

Dr. D'nar: Notice of applicability

2020-04-18T15:24:16Z

Notice of applicability

Runer112: /* Details */

2018-04-19T15:22:47Z

‎Details

Runer112 at 15:15, 19 April 2018

2018-04-19T15:15:56Z

Runer112: /* Details */

2018-04-19T15:13:09Z

‎Details

Adriweb at 14:57, 19 April 2018

2018-04-19T14:57:34Z

Adriweb at 14:56, 19 April 2018

2018-04-19T14:56:18Z

Dr. D'nar: Updated language to reflect difference between wait states and total time

2015-04-05T19:12:32Z

Updated language to reflect difference between wait states and total time

Dr. D'nar: RAM wait states update

2015-04-04T03:11:04Z

RAM wait states update

Dr. D'nar at 07:51, 3 April 2015

2015-04-03T07:51:34Z

Dr. D'nar: The text needs to be less certain-sounding.

2015-03-31T23:42:17Z

The text needs to be less certain-sounding.

← Older revision		Revision as of 15:24, 18 April 2020
Line 6:		Line 6:

	'''Function:''' Controls flash wait states. Each read from flash will have at least 5 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 9 wait state penalty, for a total of 10 clock cycles to read a byte from flash. (V/RAM gets 3 wait states for reads, and 1 waitvstate for writes, for totals of 4 and 2, respectively.)		'''Function:''' Controls flash wait states. Each read from flash will have at least 5 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 9 wait state penalty, for a total of 10 clock cycles to read a byte from flash. (V/RAM gets 3 wait states for reads, and 1 waitvstate for writes, for totals of 4 and 2, respectively.)
		+
		+	This port is only applicable to older devices which feature a [[84PCE:Ports:1000\|parallel flash chip.]]

	== Details ==		== Details ==

@@ Line 16: / Line 16: @@
 |-
 |01
-|Makes OS a little faster, perhaps 30%. Used by the C toolchain between [https://github.com/CE-Programming/toolchain/commit/76c6620b33c550637e97a8e67ae4e6a788d7d113#diff-acbd510f12643ca0895f22a9f30a5a8cR55 October 2016] and [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047#diff-acbd510f12643ca0895f22a9f30a5a8cL55 April 2017]. Occasional crashes reported on calculators across all revisions (see: fix commit message, [https://tiplanet.org/forum/viewtopic.php?f=8&t=19535 this post]). Not recommended for regular use.
+|Makes OS a little faster, perhaps 30%. Used by the C toolchain between [https://github.com/CE-Programming/toolchain/commit/76c6620b33c550637e97a8e67ae4e6a788d7d113#diff-acbd510f12643ca0895f22a9f30a5a8cR55 October 2016] and [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047#diff-acbd510f12643ca0895f22a9f30a5a8cL55 April 2017]. Occasional crashes reported on calculators across all revisions (see: [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047 fix commit message], [https://tiplanet.org/forum/viewtopic.php?f=8&t=19535 this post]). Not recommended for regular use.
 |-
 |02

@@ Line 16: / Line 16: @@
 |-
 |01
-|Makes OS a little faster, perhaps 30%. Used by the C toolchain between [https://github.com/CE-Programming/toolchain/commit/76c6620b33c550637e97a8e67ae4e6a788d7d113#diff-acbd510f12643ca0895f22a9f30a5a8cR55 October 2016] and [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047#diff-acbd510f12643ca0895f22a9f30a5a8cL55 April 2017]. Occasional crashes reported on calculators across all revisions. Not recommended for regular use.
+|Makes OS a little faster, perhaps 30%. Used by the C toolchain between [https://github.com/CE-Programming/toolchain/commit/76c6620b33c550637e97a8e67ae4e6a788d7d113#diff-acbd510f12643ca0895f22a9f30a5a8cR55 October 2016] and [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047#diff-acbd510f12643ca0895f22a9f30a5a8cL55 April 2017]. Occasional crashes reported on calculators across all revisions (see: fix commit message, [https://tiplanet.org/forum/viewtopic.php?f=8&t=19535 this post]). Not recommended for regular use.
 |-
 |02

@@ Line 16: / Line 16: @@
 |-
 |01
-|Makes OS a little faster, perhaps 30 %. Relatively unstable/crashy on several calcs.
+|Makes OS a little faster, perhaps 30%. Used by the C toolchain between [https://github.com/CE-Programming/toolchain/commit/76c6620b33c550637e97a8e67ae4e6a788d7d113#diff-acbd510f12643ca0895f22a9f30a5a8cR55 October 2016] and [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047#diff-acbd510f12643ca0895f22a9f30a5a8cL55 April 2017]. Occasional crashes reported on calculators across all revisions. Not recommended for regular use.
 |-
 |02
-|No ill-effects reported so far
+|Used by the C toolchain between [https://github.com/CE-Programming/toolchain/commit/9356661e7e57cd85b54b98a618d3a91891a59da7#diff-cc616a714307890453270fae8f0ff646R60 April 2016] and [https://github.com/CE-Programming/toolchain/commit/76c6620b33c550637e97a8e67ae4e6a788d7d113#diff-acbd510f12643ca0895f22a9f30a5a8cL54 October 2016]. Insufficient usage data was collected to determine the stability of this value.
 |-
 |03
-|No ill-effects reported so far
+|Used by the C toolchain since [https://github.com/CE-Programming/toolchain/commit/477efec0f05f530041ff09a31517fc5f92c13047#diff-acbd510f12643ca0895f22a9f30a5a8cR55 February 2017]. No crashes attributed to this value (as of April 2018).
 |-
 |04
@@ Line 31: / Line 31: @@
 |-
 |20
-|OS is unbearably sluggish, RAM program dummy loop is not slower
+|OS is unbearably sluggish
 |-
 |FF
 |Don't even bother trying to do anything
 |}

@@ Line 19: / Line 19: @@
 |-
 |02
-|Rare reports of crashes
+|No ill-effects reported so far
 |-
 |03

@@ Line 5: / Line 5: @@
 '''Memory-mapped Address:''' E00005
-'''Function:''' Controls flash wait states. Each read from flash will have at least 6 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 10 wait state penalty. (V/RAM gets 4 wait states for reads, 2 for writes.)
+'''Function:''' Controls flash wait states. Each read from flash will have at least 5 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 9 wait state penalty, for a total of 10 clock cycles to read a byte from flash. (V/RAM gets 3 wait states for reads, and 1 waitvstate for writes, for totals of 4 and 2, respectively.)
 == Details ==

@@ Line 1: / Line 1: @@
-[[Category:84PCE:Ports:By_Address|1005 - VRAM Wait States?]] [[Category:84PCE:Ports:By_Name|VRAM Wait States?]]
+[[Category:84PCE:Ports:By_Address|1005 - Flash Wait States]] [[Category:84PCE:Ports:By_Name|Flash Wait States]]
 == Synopsis ==
 '''Port Number:''' 1005
@@ Line 5: / Line 5: @@
 '''Memory-mapped Address:''' E00005
-'''Function:''' Possibly controls wait states to VRAM accesses. Or maybe flash wait states. Or maybe we have no control over any wait states whatsoever.
+'''Function:''' Controls flash wait states. Each read from flash will have at least 6 wait states, plus the number of wait states specified in this port. The OS defaults to 04 in this port, so by default, every read from flash incurs a 10 wait state penalty. (V/RAM gets 4 wait states.)
 == Details ==
@@ Line 13: / Line 13: @@
 |-
 |00
-|Instant hard crash & reset
+|Instant hard crash & reset if OS ISR is enabled
 |-
 |01
-|Makes OS a little (?&nbsp;40&nbsp;%) faster for some operations
+|Makes OS a little faster, perhaps 30 %
 |-
 |02-03