84PCE:Ports:2000 - Revision history

Jacobly at 12:07, 2 February 2018

2018-02-02T12:07:37Z

2018-02-01T20:28:57Z

‎Synopsis

2018-02-01T18:57:21Z

‎Synopsis

2018-02-01T18:40:12Z

2018-02-01T15:40:10Z

2018-02-01T14:35:20Z

Fixe link.

2018-02-01T14:33:24Z

2018-02-01T14:33:08Z

2016-09-23T11:45:30Z

2016-09-23T11:45:08Z

@@ Line 25: / Line 25: @@
 |000C-000F
 |RO
-|3CA2D5EE&nbsp;&nbsp;&nbsp;
 |32
-|Unknown
+|Mirror of the last state word
 |-
 |0010-004F

@@ Line 7: / Line 7: @@
 '''Function:''' Cryptography
-This is the SHA256 chip. It is very similar to [https://hackspire.org/index.php/Memory-mapped_I/O_ports_on_CX#CC000000_-_SHA-256_hash_generator]. The inputs are 32-bit big-endian, but TI fails to compensate for this.
+This is the SHA256 chip. It is very similar to [https://hackspire.org/index.php/Memory-mapped_I/O_ports_on_CX#CC000000_-_SHA-256_hash_generator]. The block and state are split into 32-bit little-endian words (inputs and hashes are generally displayed big-endian), but TI fails to compensate for this.
-This port is protected. Privileged ports must be [[84PCE:Ports:0006#Bit_.5B2.5D|unlocked]] to read and write to these ports. Additionally, flash must be [[84PCE:Ports:0028|unlocked]] for the chip to function.
+This port is protected. Protected ports must be [[84PCE:Ports:0006#Bit_.5B2.5D|unlocked]] to read and write to these ports. Additionally, flash must be [[84PCE:Ports:0028|unlocked]] for the chip to function.
 {|-

@@ Line 8: / Line 8: @@
 This is the SHA256 chip. It is very similar to [https://hackspire.org/index.php/Memory-mapped_I/O_ports_on_CX#CC000000_-_SHA-256_hash_generator]. The inputs are 32-bit big-endian, but TI fails to compensate for this.
-This port is protected. Privileged ports must be unlocked to read and write to these ports. Additionally, flash must be unlocked for the chip to function.
+This port is protected. Privileged ports must be [[84PCE:Ports:0006#Bit_.5B2.5D|unlocked]] to read and write to these ports. Additionally, flash must be [[84PCE:Ports:0028|unlocked]] for the chip to function.
 {|-

@@ Line 8: / Line 8: @@
 This is the SHA256 chip. It is very similar to [https://hackspire.org/index.php/Memory-mapped_I/O_ports_on_CX#CC000000_-_SHA-256_hash_generator]. The inputs are 32-bit big-endian, but TI fails to compensate for this.
-This port is protected. Privileged ports must be unlocked to read and write to these ports.
+This port is protected. Privileged ports must be unlocked to read and write to these ports. Additionally, flash must be unlocked for the chip to function.
 {|-

@@ Line 8: / Line 8: @@
 This is the SHA256 chip. It is very similar to [https://hackspire.org/index.php/Memory-mapped_I/O_ports_on_CX#CC000000_-_SHA-256_hash_generator]. The inputs are 32-bit big-endian, but TI fails to compensate for this.
-This port is protected. Privileged MMIO must be unlocked to read and write to the MMIO ports.
+This port is protected. Privileged ports must be unlocked to read and write to these ports.
 {|-

@@ Line 8: / Line 8: @@
 This is the SHA256 chip. It is very similar to [http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#CC000000_-_SHA-256_hash_generator]. The inputs are 32-bit big-endian, but TI fails to compensate for this.
-This port is protected. Flash must be unlocked to read and write from this port.
+This port is protected. Privileged MMIO must be unlocked to read and write to the mmio ports.
 {|-

@@ Line 11: / Line 11: @@
 {|-
-|<u>Port</u>&nbsp;&nbsp;&nbsp;
+|<u>Ports</u>&nbsp;&nbsp;&nbsp;
 |<u>Default</u>&nbsp;&nbsp;&nbsp;
 |<u>Bits</u>&nbsp;&nbsp;&nbsp;
 |<u>Information</u>&nbsp;&nbsp;&nbsp;
 |}