84PCE:Ports:4000 - Revision history

Calc84maniac: Add link to ST7789 LCD controller page

2024-05-30T20:41:04Z

Add link to ST7789 LCD controller page

Runer112: Mention DMA start timing

2021-08-15T05:58:49Z

Mention DMA start timing

Runer112 at 04:52, 10 October 2017

2017-10-10T04:52:39Z

Tr1p1ea: /* Synopsis */

2017-09-07T01:01:52Z

‎Synopsis

Tr1p1ea: /* Synopsis */

2017-09-07T01:00:53Z

‎Synopsis

MateoConLechuga at 12:39, 3 July 2017

2017-07-03T12:39:30Z

Jacobly: Added interrupt bits.

2017-03-02T05:51:35Z

Added interrupt bits.

Runer112: /* PL111 Register Summary */

2016-11-21T05:15:10Z

‎PL111 Register Summary

Runer112: /* PL111 Register Summary */

2016-11-21T05:13:48Z

‎PL111 Register Summary

Runer112: /* PL111 Register Summary */

2016-11-21T05:05:38Z

‎PL111 Register Summary

@@ Line 7: / Line 7: @@
 '''Function:''' LCD Controller
-The ports in this range are for accessing the LCD controller. With these ports, you can configure the LCD DMA address, change the color mode, access the palette, alter the LCD cursor, and possibly other useful things.
+The ports in this range are for accessing the Primecell PL111 LCD controller. With these ports, you can configure the LCD DMA address, change the color mode, access the palette, alter the LCD cursor, and possibly other useful things.
 Datasheet: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0293c/DDI0293.pdf
-The LCD itself appears to be the Giant GPM1421C0. Datasheet: http://beck-oled-lcd-tft-display.de/fileadmin/giant-plus/GPM1421C0.pdf
+This controller does not drive the LCD directly, but provides timing signals and pixel data to the [[84PCE:LCD_Controller|Sitronix ST7789 LCD controller]] which in turn drives the LCD.
-<br>(mirror: http://tr1p1ea.net/files/downloads/GPM1421C0.pdf)
 == PL111 Register Summary ==

@@ Line 58: / Line 58: @@
 VSW =   2 (actual = VSW + 1 =   3)
 LPP = 319 (actual = LPP + 1 = 320)</nowiki>
 <br>
 {|border="1" cellspacing="0" cellpadding="5"
 |-

@@ Line 121: / Line 121: @@
 | R/W
 | 0x00000000
-| Upper Panel Frame Base Address Register, i.e. LCD VRAM address. Only bits 8-18 have an effect; the address is masked into the 0xD00000-0xD7FF00 range.
+| Upper Panel Frame Base Address Register, i.e. LCD VRAM address. Only bits 3-18 have an effect; the address is masked into the 0xD00000-0xD7FFF8 range.
 |}
   <nowiki>TIOS Default:

@@ Line 11: / Line 11: @@
 Datasheet: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0293c/DDI0293.pdf
-The LCD itself appears to be the Giant GPM1421C0. Datasheet: http://beck-oled-lcd-tft-display.de/fileadmin/giant-plus/GPM1421C0.pdf (mirror: http://tr1p1ea.net/files/downloads/GPM1421C0.pdf)
+The LCD itself appears to be the Giant GPM1421C0. Datasheet: http://beck-oled-lcd-tft-display.de/fileadmin/giant-plus/GPM1421C0.pdf
 == PL111 Register Summary ==

@@ Line 11: / Line 11: @@
 Datasheet: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0293c/DDI0293.pdf
-The LCD itself appears to be the Giant GPM1421C0. Datasheet: http://beck-oled-lcd-tft-display.de/fileadmin/giant-plus/GPM1421C0.pdf
+The LCD itself appears to be the Giant GPM1421C0. Datasheet: http://beck-oled-lcd-tft-display.de/fileadmin/giant-plus/GPM1421C0.pdf (mirror: http://tr1p1ea.net/files/downloads/GPM1421C0.pdf)
 == PL111 Register Summary ==

@@ Line 382: / Line 382: @@
 R		= Red palette data</nowiki>
-The palette can hold 256 x 16-bit colour entries in 1555 format. The BLUE and RED values can be swapped via bit-8 of the LCDControl Register.<br>
+The palette can hold 256 x 16-bit colour entries in 1555 format. The 1 bit is the LSB of green. The BLUE and RED values can be swapped via bit-8 of the LCDControl Register.<br>
 <br>
 When 8bpp mode is enabled the LCD will utilize graphics data to index this palette and display the resultant colour - as opposed to interpreting graphics data as colours directly.<br>

@@ Line 74: / Line 74: @@
 |}
   <nowiki>TIOS Default:
-x0402093F
+x00EF7802
 PCD =   2 (actual divisor = PCD + 2 = 4)
 BCD =   0
-CPL = 239
+CPL = 239 (actual (TFT) = (CPL + 1) * 1 = 240)
 IOE =   1
 IPC =   1
@@ Line 298: / Line 298: @@
 | LCD Interrupt Clear Register
 |}
 <br>

@@ Line 31: / Line 31: @@
 x1F0A0338
-HBP = 31
+HBP = 31 (actual =        HBP + 1 =  32)
-HFP = 10
+HFP = 10 (actual =        HFP + 1 =  11)
-HSW = 3
+HSW =  3 (actual =        HSW + 1 =   4)
-PPL = 14
+PPL = 14 (actual = 16 * (PPL + 1) = 240)</nowiki>
-Actual PPL = 16 * (PPL + 1) = 240</nowiki>
 <br>
 {|border="1" cellspacing="0" cellpadding="5"
@@ Line 54: / Line 53: @@
 x0402093F
-VBP = 4
+VBP =   4
-VFP = 2
+VFP =   2
-VSW = 2
+VSW =   2 (actual = VSW + 1 =   3)
-LPP = 319
+LPP = 319 (actual = LPP + 1 = 320)</nowiki>
-Actual LPP = LPP + 1 = 320</nowiki>
 <br>
@@ Line 78: / Line 76: @@
 x0402093F
-PCD = 2
+PCD =   2
-BCD = 0
+BCD =   0
 CPL = 239
-IOE = 1
+IOE =   1
-IPC = 1
+IPC =   1
-IHS = 1
+IHS =   1
-IVS = 1
+IVS =   1
-ACB = 0
+ACB =   0
 CLKSEL = 0</nowiki>
 <br>

@@ Line 19: / Line 19: @@
 ! Base Offset
 ! Type
-! Reset Value
+! TIOS Value
 ! Description
 |-
@@ Line 28: / Line 28: @@
 | Horizontal Axis Panel Control Register
 |}
 <br>
 {|border="1" cellspacing="0" cellpadding="5"
 |-
@@ Line 47: / Line 51: @@
 | Vertical Axis Panel Control Register
 |}
 <br>
@@ Line 63: / Line 75: @@
 | Clock and Signal Polarity Control Register
 |}
 <br>
@@ Line 79: / Line 103: @@
 | Line End Control Register
 |}
 <br>
@@ Line 93: / Line 122: @@
 | R/W
 | 0x00000000
-| LCD VRAM address; controls the DMA start address. This is not restricted to so-called VRAM; it can be in regular RAM too, and possibly even flash. This must be a multiple of 8.
+| Upper Panel Frame Base Address Register, i.e. LCD VRAM address. Only bits 8-18 have an effect; the address is masked into the 0xD00000-0xD7FF00 range.
-<!-- I mean, if it's not a multiple of 8, it won't crash. It'll just bitmask down to the nearest multiple of 8. -->
 |}
 <br>
@@ Line 110: / Line 140: @@
 | R/W
 | 0x00000000
-| Upper and Lower Panel Frame Base Address Registers
+| Lower Panel Frame Base Address Register, N/A
 |}
 <br>
@@ Line 204: / Line 236: @@
   <nowiki>ld a,$2D
 ld ($E30018),a</nowiki>
 {|border="1" cellspacing="0" cellpadding="5"
@@ Line 368: / Line 401: @@
 	ret</nowiki>
 With this palette installed, high=low graphics data (from the TI-84+CSE for example) can be reused without the need for conversion. This is because the high=low colour data will now become an index to the converted 1555 palette. Note that there will be a negligible colour difference due to the loss of precision in green.
-<br>
+<br><br>
 {|border="1" cellspacing="0" cellpadding="5"