84PCE:Ports:5000 - Revision history

Calc84maniac: /* Known Sources */

2023-01-16T21:47:42Z

‎Known Sources

Jacobly: /* Known Sources */

2019-06-29T10:23:01Z

‎Known Sources

MateoConLechuga at 01:23, 27 May 2016

2016-05-27T01:23:45Z

MateoConLechuga: /* Known Sources */

2016-05-26T15:11:25Z

‎Known Sources

MateoConLechuga: /* Synopsis */

2015-11-11T05:03:04Z

‎Synopsis

Dr. D'nar at 20:59, 5 August 2015

2015-08-05T20:59:47Z

Dr. D'nar at 22:38, 4 April 2015

2015-04-04T22:38:21Z

Calc84maniac: Added more concrete information, fixed up the page

2015-04-04T21:11:32Z

Added more concrete information, fixed up the page

Calc84maniac: Added more interrupt sources

2015-04-04T06:46:01Z

Added more interrupt sources

Dr. D'nar: No longer unknown

2015-03-31T07:28:32Z

No longer unknown

@@ Line 48: / Line 48: @@
 |16
 |Added in Python Edition.
 |-
 |19

@@ Line 45: / Line 45: @@
 |15
 |Unknown, but signal seems to be constantly on
 |-
 |}

@@ Line 41: / Line 41: @@
 |-
 |13
-|[[:84PCE:Ports:8000|USB]]
+|[[:84PCE:Ports:3000|USB]]
 |-
 |15

@@ Line 39: / Line 39: @@
 |12
 |[[:84PCE:Ports:8000|Real-Time Clock]]
 |-
 |15

@@ Line 1: / Line 1: @@
 [[Category:84PCE:Ports:By_Address|5000 - Interrupt Controller]] [[Category:84PCE:Ports:By_Name|Interrupt Controller]]
 == Synopsis ==
-'''Port Number:''' 7000-705F
+'''Port Number:''' 5000-505F
 '''Memory-mapped address:''' F00000

@@ Line 29: / Line 29: @@
 |-
 |4
-|Unknown, but disabling causes freeze (might be OS timer?)
+|Probably OS timer. Frequency is controlled by bits [1:0] of [[:84PCE:Ports:0000|port 0000]].
 |-
 |10

@@ Line 85: / Line 85: @@
+|
+|
-|Ports 5020-503F are identical in function to 5000-501F. These registers do not actually trigger interrupts. Since this chip was meant for use with ARM, these ports were intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts. However, these ports can be used for other purposes such as reading the state of the ON key.
+|Ports 5020-503F are identical in function to 5000-501F. These registers do not actually trigger interrupts. Since this IP core was meant for use with ARM, these ports were intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts. However, these ports can be used for other purposes such as reading the state of the ON key.
 |-
 |5050

@@ Line 1: / Line 1: @@
-[[Category:84PCE:Ports:By_Address|5000 - Interrupts]] [[Category:84PCE:Ports:By_Name|Interrupts]]
+[[Category:84PCE:Ports:By_Address|5000 - Interrupt Controller]] [[Category:84PCE:Ports:By_Name|Interrupt Controller]]
-This port range has an interesting semi-pattern of read-only and latching ports. Some of these ports have a critical function for interrupt-handling. A partial list is below, but ports with some kind of function continue until at least 5055.
+== Synopsis ==
-It seems to be arranged in 22-bit bitfields (each occupying a little-endian 32-bit word), with each bit corresponding to a different interrupt source. Known sources so far:
+'''Memory-mapped address:''' F00000
 {|-
 |<u>Bit</u>&nbsp;&nbsp;&nbsp;
@@ Line 11: / Line 20: @@
 |-
 |1
-|Timer 1
+|[[:84PCE:Ports:7000|Timer 1]]
 |-
 |2
-|Timer 2
+|[[:84PCE:Ports:7000|Timer 2]]
 |-
 |3
-|Timer 3
+|[[:84PCE:Ports:7000|Timer 3]]
 |-
 |4
@@ Line 23: / Line 32: @@
 |-
 |10
-|Keyboard
+|[[:84PCE:Ports:A000|Keyboard]]
 |-
 |11
-|LCD Controller
+|[[:84PCE:Ports:4000|LCD Controller]]
 |-
 |12
-|RTC, perhaps? Seems to trigger on the minute by default.
+|[[:84PCE:Ports:8000|Real-Time Clock]]
 |-
 |15
@@ Line 36: / Line 45: @@
 |}
-This range is (probably?) memory-mapped to F00000.
+=== Registers ===
-−
 {|-
 |<u>Port</u>&nbsp;&nbsp;&nbsp;
@@ Line 44: / Line 52: @@
 |<u>Information</u>&nbsp;&nbsp;&nbsp;
 |-
-|[[:84PCE:Ports:5000|5000]]
+|5000
 |Read-Only
 |003FFFFF
 |Raw interrupt status (can be either raw signal or latched on signal change from low-to-high).
 |-
-|[[:84PCE:Ports:5004|5004]]
+|5004
 |00003011
 |003FFFFF
 |Interrupt enable mask.
 |-
-|[[:84PCE:Ports:5008|5008]]
+|5008
 |Write-Only
 |003FFFFF
 |Interrupt acknowledge (used by ISR), seems to only affect latched status bits.
 |-
-|[[:84PCE:Ports:500C|500C]]
+|500C
 |00000019
 |003FFFFF
 |Determines whether bits of [[:84PCE:Ports:5000|5000]] will latch. 0 means raw signal, 1 means latched.
 |-
-|[[:84PCE:Ports:5010|5010]]
+|5010
 |00000000
 |003FFFFF
 |Inverts the raw signal of the interrupts corresponding to each 1 bit. Can be used to latch on a high-to-low change.
 |-
-|[[:84PCE:Ports:5014|5014]]
+|5014
 |Read-only
 |003FFFFF
 |Masked interrupt status (used by ISR). Should be equal to ([[:84PCE:Ports:5000|5000]] & [[:84PCE:Ports:5004|5004]]).
 |-
-|5018
+|5020
-|Read-only
-|????????
-|''Ports 5018-501F may always read zero''
-|-
-|[[:84PCE:Ports:5020|5020]]
+|
+|
-|Ports 5020-503F seem to be identical in function to 5000-501F (but not mirrors). These registers do not seem to actually trigger interrupts. Assuming this chip was meant for use with ARM, this would likely have been intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts.
+|Ports 5020-503F are identical in function to 5000-501F. These registers do not actually trigger interrupts. Since this chip was meant for use with ARM, these ports were intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts. However, these ports can be used for other purposes such as reading the state of the ON key.
 |-
 |}

@@ Line 9: / Line 9: @@
 |0
 |ON Button
 |-
 |4
@@ Line 18: / Line 27: @@
 |11
 |LCD Controller
 |-
 |15

← Older revision		Revision as of 07:28, 31 March 2015
Line 1:		Line 1:
−	[[Category:84PCE:Ports:By_Address\|5000 ~~Range Unknowns~~]] [[Category:84PCE:Ports:By_Name\|~~5000 Range Unknowns]] [[Category:84PCE:Ports:Unknown\|5000 Range Unknowns~~]]	+	[[Category:84PCE:Ports:By_Address\|5000 - Interrupts]] [[Category:84PCE:Ports:By_Name\|Interrupts]]
	This port range has an interesting semi-pattern of read-only and latching ports. Some of these ports have a critical function for interrupt-handling. A partial list is below, but ports with some kind of function continue until at least 5055.		This port range has an interesting semi-pattern of read-only and latching ports. Some of these ports have a critical function for interrupt-handling. A partial list is below, but ports with some kind of function continue until at least 5055.