84PCE:Ports:6000 - Revision history

Calc84maniac: Document proper initialization sequence

2024-07-11T22:55:36Z

Document proper initialization sequence

Calc84maniac: Improve register documentation based on research, add Detailed Operation

2024-07-11T21:48:44Z

Improve register documentation based on research, add Detailed Operation

Calc84maniac: Renamed to watchdog timer and documented registers

2015-04-04T04:51:43Z

Renamed to watchdog timer and documented registers

Dr. D'nar at 22:57, 30 March 2015

2015-03-30T22:57:55Z

Dr. D'nar: Created page with "6000 - General Purpose Timer General Purpose Timer == Synopsis == '''Port Number:''' 6000-601F '''Functio..."

2015-03-27T21:14:24Z

Created page with "6000 - General Purpose Timer General Purpose Timer == Synopsis == '''Port Number:''' 6000-601F '''Functio..."

New page

[[Category:84PCE:Ports:By_Address|6000 - General Purpose Timer]] [[Category:84PCE:Ports:By_Name|General Purpose Timer]]
== Synopsis ==
'''Port Number:''' 6000-601F

'''Function:''' General purpose timer

This range of ports appears to be the new crystal timer. We seem to have only one.

← Older revision		Revision as of 22:55, 11 July 2024
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	Effectively this means that when configured with the CPU clock, the counter has a period of the load register plus 1, plus the pulse width register plus 1. When configured with the 32768Hz clock, the counter has a period of the load register, plus 1 if the pulse width register plus 2 CPU cycles exceeds the length of a 32768Hz tick (which is only possible if the CPU clock is set to 6MHz).		Effectively this means that when configured with the CPU clock, the counter has a period of the load register plus 1, plus the pulse width register plus 1. When configured with the 32768Hz clock, the counter has a period of the load register, plus 1 if the pulse width register plus 2 CPU cycles exceeds the length of a 32768Hz tick (which is only possible if the CPU clock is set to 6MHz).
		+
		+	== Watchdog Initialization ==
		+	Care should be taken when initializing the watchdog timer, because it's possible for the timer to be stopped while in pulse mode, and writing to the reload register does not switch back to counter mode. Thus, it is possible to accidentally trigger a reset or NMI when starting the timer for the first time, depending on previous usage.
		+
		+	However, it is possible to take advantage of the fact that the pulse counter being 0 will switch to counter mode, even if the timer is not enabled. But be aware that the main counter being 0 will also similarly switch to pulse mode, so ensure it is non-zero first.
		+
		+	Thus, an effective initialization order is:
		+	* Write 0 to the control register to disable the timer
		+	* Write the desired (non-zero) load value to the load register
		+	* Write B9h to the reload register to load the counter
		+	* Write 0 to the pulse width register to reload the pulse counter with 0 and switch out of pulse mode if needed
		+	* Write the desired pulse width value to the pulse width register (if the desired value is non-zero)
		+	* Write to the control register to enable the timer and any desired signals

@@ Line 16: / Line 16: @@
 ** 32-bit counter register.
 * 6004-6007 (R/W):
-** 32-bit load register. The counter is loaded with this value when it reaches 0 or the restart register is used.
+** 32-bit load register. The counter is loaded with this value after it reaches 0 or the reload register is used.
-* 6008-6009 (W):
+* 6008 (W):
-** 16-bit restart register. When the value 5AB9h is written here, the counter is restarted. The bytes can be written individually.
+** 8-bit reload register. When the value B9h is written here, the counter is reloaded with the value of the load register.
 * 600C (R/W):
 ** Bit 0: Timer enable. Set to make the counter count down.
@@ Line 26: / Line 26: @@
 ** Bit 4: Clock source. Set to 1 to use the 32768Hz clock, or 0 to use the CPU clock.
 * 6010 (R):
-** Status register. Bit 0 is set after the timer has reached 0, otherwise reset.
+** Status register. Bit 0 becomes set after the counter reaches 0 and the timer switches to pulse mode (see [[#Detailed Operation|Detailed Operation]]).
-* 6014 (W):
+* 6014-6017 (W):
-** Status clear register. Write 1 to reset bit 0 of the status register.
+** Status clear register. Write any value to any of these bytes to reset bit 0 of the status register.
 * 6018 (R/W):
-** 8-bit interrupt length register. Controls the amount of time an interrupt is signaled.
+** 8-bit pulse width register. Write with the number of CPU cycles to pulse the configured signals, minus 1 (this immediately reloads the pulse counter). Reads the current value of the pulse counter, which counts down to 0 during a pulse.
 * 601C-601F (R):
 ** 32-bit revision register. Reads a constant 0x00010602, which corresponds to revision 1.6.2.

@@ Line 1: / Line 1: @@
-[[Category:84PCE:Ports:By_Address|6000 - General Purpose Timer]] [[Category:84PCE:Ports:By_Name|General Purpose Timer]]
+[[Category:84PCE:Ports:By_Address|6000 - Watchdog Timer]] [[Category:84PCE:Ports:By_Name|Watchdog Timer]]
 == Synopsis ==
 '''Port Number:''' 6000-601F
@@ Line 5: / Line 5: @@
 '''Memory-mapped address:''' F10000
-'''Function:''' General purpose timer
+'''Function:''' Watchdog timer
-This range of ports appears to be the new crystal timer. We seem to have only one.
+This range of ports is a watchdog timer (appears to be model FTWDT010). Its primary feature is a 32-bit looping downward counter which can be set to either 32768Hz or the CPU frequency. It can also be used to reset the calculator or trigger a non-maskable interrupt (which typically will also reset the calculator). It is unknown whether it can trigger a maskable interrupt.