84PCE:Ports:D000 - Revision history

Calc84maniac: Link to the LCD controller page for command descriptions

2024-05-30T20:32:42Z

Link to the LCD controller page for command descriptions

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Calc84maniac: /* Synopsis */ Add guidance to avoid writing to a full FIFO

2024-03-02T22:25:23Z

‎Synopsis: Add guidance to avoid writing to a full FIFO

Calc84maniac: Update base clock speed

2023-10-20T06:36:14Z

Update base clock speed

Calc84maniac: /* Synopsis */

2023-04-29T15:40:20Z

‎Synopsis

Calc84maniac: Added interrupt register documentation

2023-01-17T06:34:01Z

Added interrupt register documentation

Calc84maniac: Clarify readable bits from data register

2023-01-17T03:38:14Z

Clarify readable bits from data register

Calc84maniac: Updated SPI register documentation

2023-01-16T23:14:40Z

Updated SPI register documentation

Calc84maniac: Add more descriptions to SPI controller registers

2022-03-17T19:37:44Z

Add more descriptions to SPI controller registers

Calc84maniac: Add closer matching datasheet for the LCD controller

2022-02-26T05:14:30Z

Add closer matching datasheet for the LCD controller

Zeroko: Updated based on FTSSP010 driver for Linux

2020-04-08T21:07:05Z

Updated based on FTSSP010 driver for Linux

@@ Line 51: / Line 51: @@
+|
 |FFFFFFFF
-|FIFO in/out. Writes push to the send FIFO, and reads pop from the receive FIFO.<br/>Supports up to a 32-bit data length, but when working with more than 8 bits, the low byte access must come last because it causes the push/pop of the entire entry.<br/>The upper 24 bits are latched when written to, but seem to be undefined after pushing a FIFO entry.<br/>Any read bits when the FIFO is empty or outside of the receive's configured bit length are undefined, and should be ignored/masked out.
+|FIFO in/out. Writes push to the send FIFO, and reads pop from the receive FIFO.<br/>Supports up to a 32-bit data length, but when working with more than 8 bits, the low byte access must come last because it causes the push/pop of the entire entry.<br/>The upper 24 bits are latched when written to, but seem to be undefined after pushing a FIFO entry. These bits should not be written to while the FIFO is full.<br/>Any read bits when the FIFO is empty or outside of the receive's configured bit length are undefined, and should be ignored/masked out.
 |-
 |D01C<br/>F8001C

@@ Line 26: / Line 26: @@
 |0002000B
 |007FFFFF
-|CR1: Bits 0-15 are clock divider - 1, bits 16-22 are FIFO entry data length in bits - 1.<br/>According to some drivers, bits 24-31 are padding length, but on this controller it's non-writable and seems to have no effect on transfers or timing.<br/>Base clock is likely 12 MHz (unconfirmed whether this changes with CPU speed).<br/>Sending with a clock divider of 1 to the LCD has been empirically unreliable across models, but a divider of 2 seems safe. According to LCD controller specs, receiving may require a larger divider.
+|CR1: Bits 0-15 are clock divider - 1, bits 16-22 are FIFO entry data length in bits - 1.<br/>According to some drivers, bits 24-31 are padding length, but on this controller it's non-writable and seems to have no effect on transfers or timing.<br/>Base clock is 24 MHz (unconfirmed whether this changes with CPU speed).<br/>Sending with a clock divider of 1 to the LCD has been empirically unreliable across models, but a divider of 2 seems safe. According to LCD controller specs, receiving may require a larger divider.
 |-
 |D008<br/>F80008

@@ Line 51: / Line 51: @@
+|
 |FFFFFFFF
-|FIFO in/out. Writes push to the send FIFO, and reads pop from the receive FIFO.<br/>Supports up to a 32-bit data length, but when working with more than 8 bits, the low byte access must come last because it causes the push/pop of the entire entry.<br/>The upper 24 bits are latched when written to, even after pushing a FIFO entry. This allows the same upper bits to be reused in consecutive entries even when only writing the low byte.<br/>Any read bits when the FIFO is empty or outside of the receive's configured bit length are undefined, and should be ignored/masked out.
+|FIFO in/out. Writes push to the send FIFO, and reads pop from the receive FIFO.<br/>Supports up to a 32-bit data length, but when working with more than 8 bits, the low byte access must come last because it causes the push/pop of the entire entry.<br/>The upper 24 bits are latched when written to, but seem to be undefined after pushing a FIFO entry.<br/>Any read bits when the FIFO is empty or outside of the receive's configured bit length are undefined, and should be ignored/masked out.
 |-
 |D01C<br/>F8001C

@@ Line 36: / Line 36: @@
 |00000002
 |0001F1F7
-|Status bits (read-only).<br/>Bit 0 is set if the receive FIFO is full, and Bit 1 is set if the send FIFO is <i>not</i> full (can accept more writes).<br/>Bit 2 is set if data is being sent or received, bits 4-8 are the number of queued receive FIFO entries, and bits 12-16 are the number of queued send FIFO entries.<br/>Boot code waits for bits 2 and 12-15 to be 0 before/after reading/writing.<br/>The receive FIFO seems to stop accepting data after 15 entries are full, <i>unless</i> a send forces the 16th receive. Thus, Bit 2 more reliable to detect a halted receive than Bit 0.
+|Status bits (read-only).<br/>Bit 0 is set if the receive FIFO is full, and Bit 1 is set if the send FIFO is <i>not</i> full (can accept more writes).<br/>Bit 2 is set if data is being sent or received, bits 4-8 are the number of queued receive FIFO entries, and bits 12-16 are the number of queued send FIFO entries.<br/>Boot code waits for bits 12-15 and bit 2 to be 0 (in that order) before/after reading/writing.<br/>Receiving seems to stop after 15 FIFO entries are full, unless the send FIFO is non-empty. Conversely, receiving does not stop before 15 FIFO entries are full, even if the send FIFO is empty.<br/>It's unclear what data is sent when this occurs, so it's best to disable the transfer when the send FIFO underruns.
 |-
 |D010<br/>F80010
-|00002100
+|00000021
 |0001FFBF
-|Interrupt control.
+|Interrupt control. Masked with interrupt status to generate interrupts.<br/>Bit 0: Receive FIFO overrun interrupt enable.<br/>Bit 1: Send FIFO underrun interrupt enable.<br/>Bit 2: Receive FIFO threshold interrupt enable.<br/>Bit 3: Send FIFO threshold interrupt enable.<br/>Bits 7-11: Receive FIFO threshold. The interrupt status bit is set if and only if the receive FIFO has this many queued entries or more. Ignored when set to 0.<br/>Bits 12-16: Send FIFO threshold. The interrupt status bit is set if and only if the send FIFO has this many queued entries or fewer. Ignored when set to 0.
 |-
 |D014<br/>F80014
+|
-|Interrupt status.
+|0000000F
 |-
 |D018<br/>F80018

@@ Line 51: / Line 51: @@
+|
 |FFFFFFFF
-|FIFO in/out. Writes push to the send FIFO, and reads pop from the receive FIFO.<br/>Supports up to a 32-bit data length, but when working with more than 8 bits, the low byte access must come last because it causes the push/pop of the entire entry.<br/>The upper 24 bits are latched when written to, even after pushing a FIFO entry. This allows the same upper bits to be reused in consecutive entries even when only writing the low byte.
+|FIFO in/out. Writes push to the send FIFO, and reads pop from the receive FIFO.<br/>Supports up to a 32-bit data length, but when working with more than 8 bits, the low byte access must come last because it causes the push/pop of the entire entry.<br/>The upper 24 bits are latched when written to, even after pushing a FIFO entry. This allows the same upper bits to be reused in consecutive entries even when only writing the low byte.<br/>Any read bits when the FIFO is empty or outside of the receive's configured bit length are undefined, and should be ignored/masked out.
 |-
 |D01C<br/>F8001C

@@ Line 19: / Line 19: @@
 |-
 |D000<br/>F80000
+|0000182B
-|0000F38C
+|0000FFFF
-|CR0: Boot code writes 180B/09 before/after turning on/off the lcd.
+|CR0: Bits 12-15 indicate the protocol, set the value to 1 for SPI.<br/>The selected protocol determines the read mask; the effective mask for SPI is F8EF.<br/>Boot code writes 180B/09 before/after turning on/off the lcd.
 |-
 |D004<br/>F80004
-|0000182B
+|0002000B
 |007FFFFF
-|CR1: Boot code initializes to 02000B. Bits 0-15 are clock divider - 1, bits 16-23 are data length - 1, and bits 24-31 are padding length.<br/>Base clock is likely 12 MHz (unconfirmed whether this changes with CPU speed).<br/>Sending with a clock divider of 1 seems to be within the LCD controller specs, but receiving may require a larger divider.
+|CR1: Bits 0-15 are clock divider - 1, bits 16-22 are FIFO entry data length in bits - 1.<br/>According to some drivers, bits 24-31 are padding length, but on this controller it's non-writable and seems to have no effect on transfers or timing.<br/>Base clock is likely 12 MHz (unconfirmed whether this changes with CPU speed).<br/>Sending with a clock divider of 1 to the LCD has been empirically unreliable across models, but a divider of 2 seems safe. According to LCD controller specs, receiving may require a larger divider.
 |-
 |D008<br/>F80008
-|0002000B
+|0000010C
-|00000F8F
+|00000FCF
-|CR2: Boot code initializes to 010C.<br/>Bit 0 is set to transfer data and activate the SPI chip select signal.<br/>Writing a 1 to Bit 2 clears the receive FIFO and writing a 1 to Bit 3 clears the send FIFO. Writing a 1 to Bit 6 resets the SPI controller.<br/>Bit 7 is set to enable receiving, Bit 8 is set to enable sending.
+|CR2: Bit 0 is set to transfer data and activate the SPI chip select signal.<br/>Bit 1 is set for data output enable according to some drivers, but this has no effect on LCD sends.<br/>Writing a 1 to Bit 2 clears the receive FIFO and writing a 1 to Bit 3 clears the send FIFO. Writing a 1 to Bit 6 resets the SPI controller.<br/>Bit 7 is set to enable receiving, Bit 8 is set to enable sending.<br/>Bits 9-11 are used for chip select, according to some drivers. Set to 0 for LCD sends.
 |-
 |D00C<br/>F8000C
+|00000002
-|000007F6
+|0001F1F7
-|Status bits.<br/>Bit 0 is set if the receive FIFO is full, and Bit 1 is set if the send FIFO is <i>not</i> full (can accept more writes).<br/>Bit 2 is set if data is being sent or received and bits 12-15 are the number of queued FIFO entries.<br/>Boot code waits for bits 2 and 12-15 to be 0 before/after reading/writing.
+|Status bits (read-only).<br/>Bit 0 is set if the receive FIFO is full, and Bit 1 is set if the send FIFO is <i>not</i> full (can accept more writes).<br/>Bit 2 is set if data is being sent or received, bits 4-8 are the number of queued receive FIFO entries, and bits 12-16 are the number of queued send FIFO entries.<br/>Boot code waits for bits 2 and 12-15 to be 0 before/after reading/writing.<br/>The receive FIFO seems to stop accepting data after 15 entries are full, <i>unless</i> a send forces the 16th receive. Thus, Bit 2 more reliable to detect a halted receive than Bit 0.
 |-
 |D010<br/>F80010
 |00002100
+|0001FFBF
 |Interrupt control.
 |-
@@ Line 50: / Line 50: @@
 |D018<br/>F80018
+|
+|FFFFFFFF
-|FIFO in/out. Supports up to a 32-bit data length according to spec, but the eZ80 can only read/write up to 8 bits per FIFO entry.
+|FIFO in/out. Writes push to the send FIFO, and reads pop from the receive FIFO.<br/>Supports up to a 32-bit data length, but when working with more than 8 bits, the low byte access must come last because it causes the push/pop of the entire entry.<br/>The upper 24 bits are latched when written to, even after pushing a FIFO entry. This allows the same upper bits to be reused in consecutive entries even when only writing the low byte.
 |-
 |D01C<br/>F8001C

← Older revision		Revision as of 05:14, 26 February 2022
Line 7:		Line 7:
	'''Function:''' LCD Interface		'''Function:''' LCD Interface

−	This appears to be an FTSSP010 or compatible SPI controller that interfaces with the LCD. ~~Non-extended commands from~~ [https://~~cdn-shop~~.~~adafruit~~.com/~~datasheets~~/~~ILI9340~~.pdf] ~~appear to work, but there's plenty of unknown commands used by the boot code~~.	+	This appears to be an FTSSP010 or compatible SPI controller that interfaces with the LCD. The command set seems to closely match the Sitronix ST7789 family [https://www.rhydolabz.com/documents/33/ST7789.pdf].

@@ Line 7: / Line 7: @@
 '''Function:''' LCD Interface
-This appears to be an SPI controller that interfaces with the LCD.  Non-extended commands from [https://cdn-shop.adafruit.com/datasheets/ILI9340.pdf] appear to work, but there's plenty of unknown commands used by the boot code.
+This appears to be an FTSSP010 or compatible SPI controller that interfaces with the LCD.  Non-extended commands from [https://cdn-shop.adafruit.com/datasheets/ILI9340.pdf] appear to work, but there's plenty of unknown commands used by the boot code.
@@ Line 19: / Line 19: @@
+|
 |0000F38C
-|Boot code writes 180B/09 before/after turning on/off the lcd.<br/>Bits 0-2 could be transfer size.
+|CR0: Boot code writes 180B/09 before/after turning on/off the lcd.
 |-
 |D004<br/>F80004
 |0000182B
 |007FFFFF
-|Boot code initializes to 02000B.
+|CR1: Boot code initializes to 02000B. Bits 0-15 are clock divider - 1, bits 16-23 are data length - 1, and bits 24-31 are padding length.
 |-
 |D008<br/>F80008
 |0002000B
 |00000F8F
-|Boot code initializes to 010C.<br/>Bit 0 is set to transfer data.<br/>Bit 7 is set/reset for reading/writing.
+|CR2: Boot code initializes to 010C.<br/>Bit 0 is set to transfer data.<br/>Bit 7 is set/reset for reading/writing.
 |-
 |D00C<br/>F8000C
+|
 |000007F6
-|Status bits.<br/>Bit 2 appears to be set if data is sending, and bits 12-15 the number of values queued.<br/>Boot code waits for bits 2 and 12-15 to be 0 before/after reading/writing.
+|Status bits.<br/>Bit 2 is set if data is being sent or received and bits 12-15 are the number of bits queued.<br/>Boot code waits for bits 2 and 12-15 to be 0 before/after reading/writing.
 |-
 |D010<br/>F80010
 |00002100
+|
-|Unknown
+|Interrupt control.
 |-
 |D014<br/>F80014
 |00000008
+|
-|Unknown
+|Interrupt status.
 |-
 |D018<br/>F80018
@@ Line 54: / Line 54: @@
 |0E0F0F1F
+|
-|Constant, could be an ID or status.
+|Inside reserved range. Appears to be a copy of the feature register at D064.
 |-
 |D060<br/>F80060
 |00012100
+|
-|Constant, could be an ID or status.
+|Revision (read-only)
 |-
 |D064<br/>F80064
 |0E0F0F1F
+|
-|Constant, could be an ID or status.
+|Features (read-only): 32-bit data width, 16-bit FIFOs, list of extra protocols supported.
 |}