86:Interrupts - Revision history

Zeroko: Added brief description of OS ISR & its user interrupt handler support

2021-09-21T07:01:28Z

Added brief description of OS ISR & its user interrupt handler support

Zeroko: Fixed behavior of IM 2 vectors in unused banks

2021-09-21T04:38:19Z

Fixed behavior of IM 2 vectors in unused banks

Zeroko: Created page with "Interrupts Individual interrupt sources can be enabled, disabled, or acknowledged using Port 3. When an interrupt..."

2021-09-21T04:34:04Z

Created page with "Interrupts Individual interrupt sources can be enabled, disabled, or acknowledged using Port 3. When an interrupt..."

New page

[[Category:86:General Hardware Information|Interrupts]]

Individual interrupt sources can be enabled, disabled, or acknowledged using [[86:Ports:03|Port 3]]. When an interrupt occurs, the CPU automatically masks interrupts, so there is no need to start with DI. Interrupts must be acknowledged before executing EI, or the interrupt will retrigger immediately after the instruction following the EI is executed. RET & RETI have the same effects on the TI-86, so RET can be used to save one byte.

There is no way to cause a non-maskable interrupt, so the OS does not have an NMI handler.

== Interrupt Mode 0 ==
When an interrupt occurs, the CPU treats the current bus content as an opcode & executes it. If the interrupt source was the [[86:LCD_Controller|LCD Controller]], this will be the last byte transferred by DMA. For any other interrupt source, it will be the last byte accessed by the instruction that was executing when the interrupt condition arose, either as part of the instruction itself or as a memory operand. If the resulting opcode requires additional opcode or operand bytes, they will all have the same value fetched from the address in PC without changing the value of PC. Under normal circumstances, IM 0 is likely to result in a crash.

== Interrupt Mode 1 ==
When an interrupt occurs, the CPU pushes the return address & then jumps to address 0038h. If the ROM is disabled at the time (see bit 6 of [[86:Ports:04|Port 4]]), the calculator will likely crash.

== Interrupt Mode 2 ==
When an interrupt occurs, the CPU treats the current bus content as the lower 8 bits of an address, with the upper 8 bits being the value of the I register. Regardless of interrupt source, the bus content will be the last byte accessed (either as part of the opcode or as a memory operand) by the instruction that was executing when the interrupt condition arose, because if [[86:LCD_Controller#DMA|LCD DMA]] occurs, it takes place after the CPU reads the previous bus content. The CPU then pushes the return address & jumps to the address stored at the address saved earlier. If either or both of the bytes of this new address are read from an [[86:Memory_Mapping#Unused_Banks|unused bank]], their value will be the lower 8 bits of the return address.

← Older revision		Revision as of 04:38, 21 September 2021
Line 12:		Line 12:

	== Interrupt Mode 2 ==		== Interrupt Mode 2 ==
−	When an interrupt occurs, the CPU treats the current bus content as the lower 8 bits of an address, with the upper 8 bits being the value of the I register. Regardless of interrupt source, the bus content will be the last byte accessed (either as part of the opcode or as a memory operand) by the instruction that was executing when the interrupt condition arose, because if [[86:LCD_Controller#DMA\|LCD DMA]] occurs, it takes place after the CPU reads the previous bus content. The CPU then pushes the return address & jumps to the address stored at the address saved earlier. If ~~either~~ or both of the bytes of this new address are read from an [[86:Memory_Mapping#Unused_Banks\|unused bank]], their value will be the lower 8 bits of the return address.	+	When an interrupt occurs, the CPU treats the current bus content as the lower 8 bits of an address, with the upper 8 bits being the value of the I register. Regardless of interrupt source, the bus content will be the last byte accessed (either as part of the opcode or as a memory operand) by the instruction that was executing when the interrupt condition arose, because if [[86:LCD_Controller#DMA\|LCD DMA]] occurs, it takes place after the CPU reads the previous bus content. The CPU then pushes the return address & jumps to the address stored at the address saved earlier. If the first or both of the bytes of this new address are read from an [[86:Memory_Mapping#Unused_Banks\|unused bank]], their value will be the lower 8 bits of the return address. If just the second byte is read from an unused bank, its value will be the same as the first.

@@ Line 9: / Line 9: @@
 == Interrupt Mode 1 ==
-When an interrupt occurs, the CPU pushes the return address & then jumps to address 0038h. If the ROM is disabled at the time (see bit 6 of [[86:Ports:04|Port 4]]), the calculator will likely crash.
+When an interrupt occurs, the CPU pushes the return address & then jumps to address 0038h. Note that ROM access should not be disabled (see bit 6 of [[86:Ports:04|Port 4]]) while IM 1 is set & interrupts are enabled, or the calculator will likely crash.
 == Interrupt Mode 2 ==
 When an interrupt occurs, the CPU treats the current bus content as the lower 8 bits of an address, with the upper 8 bits being the value of the I register. Regardless of interrupt source, the bus content will be the last byte accessed (either as part of the opcode or as a memory operand) by the instruction that was executing when the interrupt condition arose, because if [[86:LCD_Controller#DMA|LCD DMA]] occurs, it takes place after the CPU reads the previous bus content. The CPU then pushes the return address & jumps to the address stored at the address saved earlier. If the first or both of the bytes of this new address are read from an [[86:Memory_Mapping#Unused_Banks|unused bank]], their value will be the lower 8 bits of the return address. If just the second byte is read from an unused bank, its value will be the same as the first.