Difference between revisions of "83:Ports:04"
From WikiTI
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(Added memory map info) |
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| − | [[Category:83:Ports:By_Address|04 - Timer Interrupt Frequency]] [[Category:83:Ports:By_Name|Timer Interrupt Frequency]] | + | [[Category:83:Ports:By_Address|04 - Timer Interrupt Frequency / Memory Map]] [[Category:83:Ports:By_Name|Timer Interrupt Frequency / Memory Map]] |
== Synopsis == | == Synopsis == | ||
'''Port Number:''' 04h | '''Port Number:''' 04h | ||
| − | '''Function:''' Timer Interrupt Frequency | + | '''Function:''' Timer Interrupt Frequency and Memory Map Control |
| − | This port controls the frequency of the hardware timer. | + | This port controls the frequency of the hardware timer and the memory map mode. |
=== Read Values === | === Read Values === | ||
| Line 11: | Line 11: | ||
=== Write Values === | === Write Values === | ||
| − | * Bit 0 | + | * Bit 0 reset to select memory map mode 0. In mode 0 the RAM and ROM is mapped to CPU memory as follows: |
| + | ** Address 0000h ~ 3FFFh: ROM Page 0 | ||
| + | ** Address 4000h ~ 7FFFh: Swappable (Page selected in [[83:Ports:00]]/[[83:Ports:02]]) | ||
| + | ** Address 8000h ~ BFFFh: RAM Page 1 | ||
| + | ** Address C000h ~ FFFFh: RAM Page 0 | ||
| + | * Bit 0 set to select memory map mode 1. In mode 1 the RAM and ROM is mapped to CPU memory as follows: | ||
| + | ** Address 0000h ~ 3FFFh: ROM Page 0 | ||
| + | ** Address 4000h ~ 7FFFh: RAM Page 0 | ||
| + | ** Address 8000h ~ BFFFh: Swappable (Page selected in [[83:Ports:00]]/[[83:Ports:02]]) | ||
| + | ** Address C000h ~ FFFFh: RAM Page 1 | ||
* Bits 1 and 2 control the hardware timer frequency. Setting both 0 sets the timer to the fastest speed, and both 1 is the slowest speed. The normal speed is with both bits 1. | * Bits 1 and 2 control the hardware timer frequency. Setting both 0 sets the timer to the fastest speed, and both 1 is the slowest speed. The normal speed is with both bits 1. | ||
* Bit 3: Unused? Always 0. | * Bit 3: Unused? Always 0. | ||
* Bit 4: Unused? Always 1. | * Bit 4: Unused? Always 1. | ||
* Bit 5-7: Unknown, but definitely used. | * Bit 5-7: Unknown, but definitely used. | ||
| + | |||
| + | == Comments == | ||
| + | The calculator uses mode 0 for normal operation. If you change the memory map mode be sure to change it back before returning control. | ||
Revision as of 03:00, 2 April 2005
Synopsis
Port Number: 04h
Function: Timer Interrupt Frequency and Memory Map Control
This port controls the frequency of the hardware timer and the memory map mode.
Read Values
This is a mirror of the link port.
Write Values
- Bit 0 reset to select memory map mode 0. In mode 0 the RAM and ROM is mapped to CPU memory as follows:
- Address 0000h ~ 3FFFh: ROM Page 0
- Address 4000h ~ 7FFFh: Swappable (Page selected in 83:Ports:00/83:Ports:02)
- Address 8000h ~ BFFFh: RAM Page 1
- Address C000h ~ FFFFh: RAM Page 0
- Bit 0 set to select memory map mode 1. In mode 1 the RAM and ROM is mapped to CPU memory as follows:
- Address 0000h ~ 3FFFh: ROM Page 0
- Address 4000h ~ 7FFFh: RAM Page 0
- Address 8000h ~ BFFFh: Swappable (Page selected in 83:Ports:00/83:Ports:02)
- Address C000h ~ FFFFh: RAM Page 1
- Bits 1 and 2 control the hardware timer frequency. Setting both 0 sets the timer to the fastest speed, and both 1 is the slowest speed. The normal speed is with both bits 1.
- Bit 3: Unused? Always 0.
- Bit 4: Unused? Always 1.
- Bit 5-7: Unknown, but definitely used.
Comments
The calculator uses mode 0 for normal operation. If you change the memory map mode be sure to change it back before returning control.
