Difference between revisions of "84PCE:Ports:2000"

From WikiTI
Jump to: navigation, search
(Synopsis)
Line 11: Line 11:
  
 
{|-
 
{|-
|<u>Port</u>&nbsp;&nbsp;&nbsp;
+
|<u>Ports</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Type</u>&nbsp;&nbsp;&nbsp;
 
|<u>Default</u>&nbsp;&nbsp;&nbsp;
 
|<u>Default</u>&nbsp;&nbsp;&nbsp;
 
|<u>Bits</u>&nbsp;&nbsp;&nbsp;
 
|<u>Bits</u>&nbsp;&nbsp;&nbsp;
 
|<u>Information</u>&nbsp;&nbsp;&nbsp;
 
|<u>Information</u>&nbsp;&nbsp;&nbsp;
 +
|-
 +
|0000
 +
|R/W
 +
|
 +
|8
 +
|Control
 +
|-
 +
|000C-000F
 +
|RO
 +
|3CA2D5EE&nbsp;&nbsp;&nbsp;
 +
|32
 +
|Unknown
 +
|-
 +
|0010-0050
 +
|R/W
 +
|
 +
|512
 +
|SHA256 block
 +
|-
 +
|0060-007F
 +
|RO
 +
|
 +
|256
 +
|SHA256 state
 
|}
 
|}

Revision as of 03:45, 23 September 2016

Synopsis

Port Number: 2000-2???

Memory-mapped Address: E10000-E1????

Function: Cryptography

This is the SHA256 chip. It is very similar to [1]. The inputs are 32-bit big-endian, but TI fails to compensate for this. This port is protected. Flash must be unlocked to read and write from this port.

Ports    Type    Default    Bits    Information   
0000 R/W 8 Control
000C-000F RO 3CA2D5EE    32 Unknown
0010-0050 R/W 512 SHA256 block
0060-007F RO 256 SHA256 state