Difference between revisions of "84PCE:Ports:2000"
From WikiTI
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This is the SHA256 chip. It is very similar to [http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#CC000000_-_SHA-256_hash_generator]. The inputs are 32-bit big-endian, but TI fails to compensate for this. | This is the SHA256 chip. It is very similar to [http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#CC000000_-_SHA-256_hash_generator]. The inputs are 32-bit big-endian, but TI fails to compensate for this. | ||
| − | This port is protected. | + | This port is protected. Privileged MMIO must be unlocked to read and write to the mmio ports. |
{|- | {|- | ||
Revision as of 06:33, 1 February 2018
Synopsis
Port Number: 2000-2???
Memory-mapped Address: E10000-E1????
Function: Cryptography
This is the SHA256 chip. It is very similar to [1]. The inputs are 32-bit big-endian, but TI fails to compensate for this. This port is protected. Privileged MMIO must be unlocked to read and write to the mmio ports.
| Ports | Type | Default | Bits | Information |
| 0000 | R/W | 8 | Control | |
| 000C-000F | RO | 3CA2D5EE | 32 | Unknown |
| 0010-004F | R/W | 512 | SHA256 block | |
| 0060-007F | RO | 256 | SHA256 state |
