Difference between revisions of "83Plus:Ports:2F"
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| − | [[Category:83Plus:Ports:By Address|2F - LCD Wait Delay]] | + | [[Category:83Plus:Ports:By Address|2F - LCD Wait Delay/Crystal Timer Adjust]] |
| − | [[Category:83Plus:Ports:By Name|LCD Wait Delay]] | + | [[Category:83Plus:Ports:By Name|LCD Wait Delay/Crystal Timer Adjust]] |
{{SE-Only Port|07}} | {{SE-Only Port|07}} | ||
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'''Port Number:''' 2Fh | '''Port Number:''' 2Fh | ||
| − | '''Function:''' LCD Wait Delay | + | '''Function:''' LCD Wait Delay/Crystal Timer Adjust |
| − | After every write to the LCD bit 1 of [[83Plus:Ports:02|port 2]] resets for a certain amount of time. This port | + | After every write to the LCD bit 1 of [[83Plus:Ports:02|port 2]] resets for a certain amount of time based on the current cpu speed and if the calculator is in hi speed mode. This port is used to adjust the LCD delay to be the same amount of wallclock time no matter what speed setting the CPU is in, as if it was operating in 6MHz mode. The three bit groupings below define the amount to divide the system clock by. This is nominally in increments of 64 T-states, so I'm not sure where the -16 offset comes from. |
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| + | This additionally controls a divisor for the crystal timers in mode 3. 0 means divide by 1 (no divisor), 1 means divide by 2, 2 means divide by 3, &c. No divisor is applied for CPU speed 0. | ||
=== Read Values === | === Read Values === | ||
| − | * This port reads the last | + | * This port reads the last value written to it. |
=== Write Values === | === Write Values === | ||
| − | * Bits | + | * Bits 0-1 control the amount of tstates to wait when port 20 contains 1. The following values tell the number of tstates. |
| − | ** 00 = | + | ** 00 = 048 tstates |
| − | ** 01 = | + | ** 01 = 112 tstates |
| − | ** 10 = | + | ** 10 = 176 tstates |
| − | ** 11 = | + | ** 11 = 240 tstates |
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| − | * Bits | + | * Bits 2-4 control the amount of tstates to wait when port 20 contains 2. The following values tell the number of tstates. |
| − | ** 000 = | + | ** 000 = 048 tstates |
| − | ** 001 = | + | ** 001 = 112 tstates |
| − | ** 010 = | + | ** 010 = 176 tstates |
| − | ** 011 = | + | ** 011 = 240 tstates |
| − | ** 100 = | + | ** 100 = 304 tstates |
| − | ** 101 = | + | ** 101 = 368 tstates |
| − | ** 110 = | + | ** 110 = 432 tstates |
| − | ** 111 = | + | ** 111 = 496 tstates |
| + | * Bits 5-7 control the amount of tstates to wait when port 20 contains 3. The following values tell the number of tstates. | ||
| + | ** 000 = 048 tstates | ||
| + | ** 001 = 112 tstates | ||
| + | ** 010 = 176 tstates | ||
| + | ** 011 = 240 tstates | ||
| + | ** 100 = 304 tstates | ||
| + | ** 101 = 368 tstates | ||
| + | ** 110 = 432 tstates | ||
| + | ** 111 = 496 tstates | ||
== Comments == | == Comments == | ||
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This value really shouldn't be changed. TI-OS depends on this being set high enough to function for the LCD delay. | This value really shouldn't be changed. TI-OS depends on this being set high enough to function for the LCD delay. | ||
| − | Also the 83+SE has this port set to 4A as | + | Also the 83+SE has this port set to 4A as default, the 84+(SE) has this port set to 4B as default. |
== Credits and Contributions == | == Credits and Contributions == | ||
* '''James Montelongo''' | * '''James Montelongo''' | ||
Latest revision as of 15:30, 3 March 2020
| This port only exists as a distinct port on the TI-83 Plus Silver Edition, the TI-84 Plus, and the TI-84 Plus Silver Edition. On the standard TI-83 Plus, it acts as a shadow of port 07. |
Synopsis
Port Number: 2Fh
Function: LCD Wait Delay/Crystal Timer Adjust
After every write to the LCD bit 1 of port 2 resets for a certain amount of time based on the current cpu speed and if the calculator is in hi speed mode. This port is used to adjust the LCD delay to be the same amount of wallclock time no matter what speed setting the CPU is in, as if it was operating in 6MHz mode. The three bit groupings below define the amount to divide the system clock by. This is nominally in increments of 64 T-states, so I'm not sure where the -16 offset comes from.
This additionally controls a divisor for the crystal timers in mode 3. 0 means divide by 1 (no divisor), 1 means divide by 2, 2 means divide by 3, &c. No divisor is applied for CPU speed 0.
Read Values
- This port reads the last value written to it.
Write Values
- Bits 0-1 control the amount of tstates to wait when port 20 contains 1. The following values tell the number of tstates.
- 00 = 048 tstates
- 01 = 112 tstates
- 10 = 176 tstates
- 11 = 240 tstates
- Bits 2-4 control the amount of tstates to wait when port 20 contains 2. The following values tell the number of tstates.
- 000 = 048 tstates
- 001 = 112 tstates
- 010 = 176 tstates
- 011 = 240 tstates
- 100 = 304 tstates
- 101 = 368 tstates
- 110 = 432 tstates
- 111 = 496 tstates
- Bits 5-7 control the amount of tstates to wait when port 20 contains 3. The following values tell the number of tstates.
- 000 = 048 tstates
- 001 = 112 tstates
- 010 = 176 tstates
- 011 = 240 tstates
- 100 = 304 tstates
- 101 = 368 tstates
- 110 = 432 tstates
- 111 = 496 tstates
Comments
This value really shouldn't be changed. TI-OS depends on this being set high enough to function for the LCD delay.
Also the 83+SE has this port set to 4A as default, the 84+(SE) has this port set to 4B as default.
Credits and Contributions
- James Montelongo
