Difference between revisions of "83Plus:Ports:2E"

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(Added info from lcd delay ports)
m (More info from the_mad_joob. Maybe consider making him an account :D.)
 
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[[Category:83Plus:Ports:By Address|2E - CPU Speed Adjustment]] [[Category:83Plus:Ports:By Name|CPU Speed Adjustment]]
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[[Category:83Plus:Ports:By Address|2E - Memory Access Delay]] [[Category:83Plus:Ports:By Name|Memory Access Delay]]
 
{{SE-Only Port|06}}
 
{{SE-Only Port|06}}
  
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'''Port Number:''' 2Eh
 
'''Port Number:''' 2Eh
  
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'''Function:''' CPU Speed Adjustment
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'''Function:''' Memory Access Delay
  
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Bits 4 and 5 can adjust the CPU speed to a certain degree. In order for the speed adjustment to work bit 1 must be set in the appropriate LCD Delay port according to the contents of port 20. In other words, if you wish to adjust the speed at 6mhz you must set bit 1 of port 29. Other bits of this port 2E may effect the speed but nothing significant.  The default value for this port is 45h on the TI-84 Plus Silver Edition and 44h on the TI-83 Plus Silver Edition.
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This port will add a 1 cycle delay for certain types of reads for the ram or the flash. This port's effect is enabled by the lcd delay port currently selected by the current CPU speed.
  
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=== Read Values (bits 5-4)===
 
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* 00: The CPU is running at normal speed (100%)
 
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* 01: The CPU is running at ~90% of normal speed
 
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* 10: The CPU is running at ~95% of normal speed
 
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* 11: The CPU is running at ~86% of normal speed
 
  
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==To enable by the LCD Ports==
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* Bit 0 of the LCD ports (depending on current CPU speed mode) enable the effects of the flash delay controlled be 2E.
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* Bit 1 of the LCD ports (depending on current CPU speed mode) enable the effects of the ram delay controlled be 2E.
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== Read and Write Values of port 2E==
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* Bits 0-2 of port 2E affect the flash reads and (attempted) writes.
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** Bit 0 adds a clock for every opcode read from the flash.
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** Bit 1 adds a clock for every non-opcode read from the flash.
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** Bit 2 adds a clock for every (attempted) write to the flash.
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* Bits 4-6 of port 2E affect the ram reads and writes.
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** Bit 4 adds a clock for every opcode read from the ram.
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** Bit 5 adds a clock for every non-opcode read from the ram.
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** Bit 6 adds a clock for every write to the ram.
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* Bits 3 and 7 are not used in port 2E, though they can be toggled.
  
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=== Write Values (bits 5-4)===
 
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* 00: Set the CPU to run at 100% of normal speed
 
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* 01: Set the CPU to run at ~90% of normal speed
 
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* 10: Set the CPU to run at ~95% of normal speed
 
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* 11: Set the CPU to run at ~86% of normal speed
 
  
 
== Comments ==
 
== Comments ==
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With bits 0 & 4, extra clock cycle are doubled if the instruction is prefixed.
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We can safely deduct that the port adds a clock cycle each time the R register is incremented.
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Why this port is necessary is unknown, however it is set to 44 on the 83+SE and 45 on the 84+(SE).
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This port is not available on the normal TI-83+. On the normal TI-83+ this port is a shadow of [[83Plus:Ports:06|Port 06h]].
 
This port is not available on the normal TI-83+. On the normal TI-83+ this port is a shadow of [[83Plus:Ports:06|Port 06h]].
  
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== Example ==
 
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<nowiki>
 
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ld a,0
 
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out (20h),a    ;would be 6mhz
 
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in a,(29h)
 
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or 2          ;set bit 1
 
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out (29h),a
 
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ld a,74h      ;Set the CPU to ~5.1 MHz
 
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out (2Eh),a
 
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</nowiki>
 
  
 
== Credits and Contributions ==
 
== Credits and Contributions ==
 
* '''Michael Vincent:''' Documentation found [http://michaelv.org/programs/calcs/ports/port2e.html here].
 
* '''Michael Vincent:''' Documentation found [http://michaelv.org/programs/calcs/ports/port2e.html here].
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* '''James Montelongo'''
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* '''Ben Moody'''
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* '''the_mad_joob'''

Latest revision as of 10:17, 9 December 2020

This port only exists as a distinct port on the TI-83 Plus Silver Edition, the TI-84 Plus, and the TI-84 Plus Silver Edition. On the standard TI-83 Plus, it acts as a shadow of port 06.

Synopsis

Port Number: 2Eh

Function: Memory Access Delay

This port will add a 1 cycle delay for certain types of reads for the ram or the flash. This port's effect is enabled by the lcd delay port currently selected by the current CPU speed.


To enable by the LCD Ports

  • Bit 0 of the LCD ports (depending on current CPU speed mode) enable the effects of the flash delay controlled be 2E.
  • Bit 1 of the LCD ports (depending on current CPU speed mode) enable the effects of the ram delay controlled be 2E.


Read and Write Values of port 2E

  • Bits 0-2 of port 2E affect the flash reads and (attempted) writes.
    • Bit 0 adds a clock for every opcode read from the flash.
    • Bit 1 adds a clock for every non-opcode read from the flash.
    • Bit 2 adds a clock for every (attempted) write to the flash.
  • Bits 4-6 of port 2E affect the ram reads and writes.
    • Bit 4 adds a clock for every opcode read from the ram.
    • Bit 5 adds a clock for every non-opcode read from the ram.
    • Bit 6 adds a clock for every write to the ram.
  • Bits 3 and 7 are not used in port 2E, though they can be toggled.


Comments

With bits 0 & 4, extra clock cycle are doubled if the instruction is prefixed. We can safely deduct that the port adds a clock cycle each time the R register is incremented.

Why this port is necessary is unknown, however it is set to 44 on the 83+SE and 45 on the 84+(SE).

This port is not available on the normal TI-83+. On the normal TI-83+ this port is a shadow of Port 06h.


Credits and Contributions

  • Michael Vincent: Documentation found here.
  • James Montelongo
  • Ben Moody
  • the_mad_joob
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