Difference between revisions of "83Plus:Ports:2E"
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| − | [[Category:83Plus:Ports:By Address|2E - | + | [[Category:83Plus:Ports:By Address|2E - Memory Access Delay]] [[Category:83Plus:Ports:By Name|Memory Access Delay]] |
{{SE-Only Port|06}} | {{SE-Only Port|06}} | ||
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'''Port Number:''' 2Eh | '''Port Number:''' 2Eh | ||
| − | '''Function:''' | + | '''Function:''' Memory Access Delay |
| − | This port will add a 1 cycle delay for certain types of reads for the ram or the flash. This port's | + | This port will add a 1 cycle delay for certain types of reads for the ram or the flash. This port's effect is enabled by the lcd delay port currently selected by the current CPU speed. |
==To enable by the LCD Ports== | ==To enable by the LCD Ports== | ||
| − | * Bit 0 of the LCD ports (depending on current CPU speed mode) enable the effects of the flash delay | + | * Bit 0 of the LCD ports (depending on current CPU speed mode) enable the effects of the flash delay controlled be 2E. |
| − | * Bit 1 of the LCD ports (depending on current CPU speed mode) enable the effects of the ram delay | + | * Bit 1 of the LCD ports (depending on current CPU speed mode) enable the effects of the ram delay controlled be 2E. |
| Line 19: | Line 19: | ||
** Bit 0 adds a clock for every opcode read from the flash. | ** Bit 0 adds a clock for every opcode read from the flash. | ||
** Bit 1 adds a clock for every non-opcode read from the flash. | ** Bit 1 adds a clock for every non-opcode read from the flash. | ||
| − | ** Bit 2 adds a clock for every ( | + | ** Bit 2 adds a clock for every (attempted) write to the flash. |
* Bits 4-6 of port 2E affect the ram reads and writes. | * Bits 4-6 of port 2E affect the ram reads and writes. | ||
** Bit 4 adds a clock for every opcode read from the ram. | ** Bit 4 adds a clock for every opcode read from the ram. | ||
| Line 28: | Line 28: | ||
== Comments == | == Comments == | ||
| − | + | With bits 0 & 4, extra clock cycle are doubled if the instruction is prefixed. | |
| + | We can safely deduct that the port adds a clock cycle each time the R register is incremented. | ||
| − | + | Why this port is necessary is unknown, however it is set to 44 on the 83+SE and 45 on the 84+(SE). | |
| + | This port is not available on the normal TI-83+. On the normal TI-83+ this port is a shadow of [[83Plus:Ports:06|Port 06h]]. | ||
| Line 38: | Line 40: | ||
* '''James Montelongo''' | * '''James Montelongo''' | ||
* '''Ben Moody''' | * '''Ben Moody''' | ||
| + | * '''the_mad_joob''' | ||
Latest revision as of 10:17, 9 December 2020
| This port only exists as a distinct port on the TI-83 Plus Silver Edition, the TI-84 Plus, and the TI-84 Plus Silver Edition. On the standard TI-83 Plus, it acts as a shadow of port 06. |
Contents
Synopsis
Port Number: 2Eh
Function: Memory Access Delay
This port will add a 1 cycle delay for certain types of reads for the ram or the flash. This port's effect is enabled by the lcd delay port currently selected by the current CPU speed.
To enable by the LCD Ports
- Bit 0 of the LCD ports (depending on current CPU speed mode) enable the effects of the flash delay controlled be 2E.
- Bit 1 of the LCD ports (depending on current CPU speed mode) enable the effects of the ram delay controlled be 2E.
Read and Write Values of port 2E
- Bits 0-2 of port 2E affect the flash reads and (attempted) writes.
- Bit 0 adds a clock for every opcode read from the flash.
- Bit 1 adds a clock for every non-opcode read from the flash.
- Bit 2 adds a clock for every (attempted) write to the flash.
- Bits 4-6 of port 2E affect the ram reads and writes.
- Bit 4 adds a clock for every opcode read from the ram.
- Bit 5 adds a clock for every non-opcode read from the ram.
- Bit 6 adds a clock for every write to the ram.
- Bits 3 and 7 are not used in port 2E, though they can be toggled.
Comments
With bits 0 & 4, extra clock cycle are doubled if the instruction is prefixed. We can safely deduct that the port adds a clock cycle each time the R register is incremented.
Why this port is necessary is unknown, however it is set to 44 on the 83+SE and 45 on the 84+(SE).
This port is not available on the normal TI-83+. On the normal TI-83+ this port is a shadow of Port 06h.
Credits and Contributions
- Michael Vincent: Documentation found here.
- James Montelongo
- Ben Moody
- the_mad_joob
