Difference between revisions of "84PCE:Ports:Control"
From WikiTI
(→Port Address Space) |
(Fix OS Timer Control and CPU Speed Control being swapped) |
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|[[:84PCE:Ports:0000|0000]] | |[[:84PCE:Ports:0000|0000]] | ||
|03 | |03 | ||
| − | | | + | |OS Timer Control |
|- | |- | ||
|[[:84PCE:Ports:0001|0001]] | |[[:84PCE:Ports:0001|0001]] | ||
|03 | |03 | ||
| − | | | + | |CPU Speed Control |
|- | |- | ||
|[[:84PCE:Ports:0002|0002]] | |[[:84PCE:Ports:0002|0002]] | ||
Latest revision as of 23:44, 23 April 2021
Synopsis
Port Number: 0000-0fff
Function: Master Control
This port range is used to configure and control important things; possibly the reason why it does not have a memory-mapped address. It is mirrored every 0x100 bytes.
If a port is not listed; it indicates that writes have no effect and do not latch, and that reads are 0. Note that this may not be true one hundred percent.
Port Address Space
| Port | Default | Information |
| 0000 | 03 | OS Timer Control |
| 0001 | 03 | CPU Speed Control |
| 0002 | Read only, value can change | |
| 0003 | 00 | Hardware ID |
| 0005 | 76 | Set bit 5 to freeze, bit 6 affects backlight |
| 0006 | 03 | Display refresh |
| 0007 | B7 | GPIO A DIR |
| 0008 | 7F | GPIO A IN |
| 0009 | 37 | GPIO A OUT |
| 000A | FD | GPIO B DIR |
| 000B | F8 | GPIO B IN |
| 000C | 00 | GPIO B OUT |
| 000D | FF | Power control |
| 000E | 0A | Latches value written |
| 000F | 42 | High nibble may be a status, low 2 bits latch value written |
| 001C | 80 | Cannot change value |
| 001D | A7 | Privileged address |
| 0020 | 7C | Memory protection |
| 0028 | Bit 1 is always 0 | |
| 0029 | 00 | Bit 0 latches value written |
| 002A | 70 | Latches value written |
| 002B | FE | Latches value written |
| 002C | Ports 002C-0031 latch value written | |
| 0032 | Latches value written | |
| 0033 | Latches value written | |
| 0034 | Latches value written | |
| 0035 | Latches value written | |
| 0036 | Ports 0036-0039 latch value written |
