Difference between revisions of "84PCE:Ports:5000"

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(Updated 5010)
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[[Category:84PCE:Ports:By_Address|5000 Range Unknowns]] [[Category:84PCE:Ports:By_Name|5000 Range Unknowns]] [[Category:84PCE:Ports:Unknown|5000 Range Unknowns]]
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[[Category:84PCE:Ports:By_Address|5000 - Interrupt Controller]] [[Category:84PCE:Ports:By_Name|Interrupt Controller]]
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This port range has an interesting semi-pattern of read-only and latching ports. Some of these ports have a critical function for interrupt-handling. A partial list is below, but ports with some kind of function continue until at least 5055.
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== Synopsis ==
 +
'''Port Number:''' 5000-505F
  
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It seems to be arranged in 22-bit bitfields (each occupying a little-endian 32-bit word), with each bit corresponding to a different interrupt source. Known sources so far:
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'''Memory-mapped address:''' F00000
 +
 
 +
'''Function:''' Interrupt Controller
 +
 
 +
This port range is used to configure and control interrupts (appears to be model FTINTC010). There are two sets of interrupt control registers, but only the first actually triggers interrupts on the eZ80.
 +
 
 +
It is arranged in 22-bit bitfields (each occupying a little-endian 32-bit word), with each bit corresponding to a different interrupt source.
 +
 
 +
=== Known Sources ===
 
{|-
 
{|-
 
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
Line 9: Line 18:
 
|0
 
|0
 
|ON Button
 
|ON Button
 +
|-
 +
|1
 +
|[[:84PCE:Ports:7000|Timer 1]]
 +
|-
 +
|2
 +
|[[:84PCE:Ports:7000|Timer 2]]
 +
|-
 +
|3
 +
|[[:84PCE:Ports:7000|Timer 3]]
 
|-
 
|-
 
|4
 
|4
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|Unknown, but disabling causes freeze (might be OS timer?)
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|Probably OS timer. Frequency is controlled by bits [1:0] of [[:84PCE:Ports:0000|port 0000]].
 
|-
 
|-
 
|10
 
|10
−
|Keyboard
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|[[:84PCE:Ports:A000|Keyboard]]
 
|-
 
|-
 
|11
 
|11
−
|LCD Controller
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|[[:84PCE:Ports:4000|LCD Controller]]
 +
|-
 +
|12
 +
|[[:84PCE:Ports:8000|Real-Time Clock]]
 +
|-
 +
|13
 +
|[[:84PCE:Ports:3000|USB]]
 
|-
 
|-
 
|15
 
|15
 
|Unknown, but signal seems to be constantly on
 
|Unknown, but signal seems to be constantly on
 +
|-
 +
|16
 +
|Added in Python Edition.
 +
|-
 +
|18
 +
|[[:84PCE:Ports:D000|SPI]]
 +
|-
 +
|19
 +
|Added in Python Edition.
 
|-
 
|-
 
|}
 
|}
  
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This range is (probably?) memory-mapped to F00000.
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=== Registers ===
−
 
+
 
{|-
 
{|-
 
|<u>Port</u>&nbsp;&nbsp;&nbsp;
 
|<u>Port</u>&nbsp;&nbsp;&nbsp;
Line 32: Line 64:
 
|<u>Information</u>&nbsp;&nbsp;&nbsp;
 
|<u>Information</u>&nbsp;&nbsp;&nbsp;
 
|-
 
|-
−
|[[:84PCE:Ports:5000|5000]]
+
|5000
 
|Read-Only
 
|Read-Only
 
|003FFFFF
 
|003FFFFF
 
|Raw interrupt status (can be either raw signal or latched on signal change from low-to-high).
 
|Raw interrupt status (can be either raw signal or latched on signal change from low-to-high).
 
|-
 
|-
−
|[[:84PCE:Ports:5004|5004]]
+
|5004
 
|00003011
 
|00003011
 
|003FFFFF
 
|003FFFFF
 
|Interrupt enable mask.
 
|Interrupt enable mask.
 
|-
 
|-
−
|[[:84PCE:Ports:5008|5008]]
+
|5008
 
|Write-Only
 
|Write-Only
 
|003FFFFF
 
|003FFFFF
 
|Interrupt acknowledge (used by ISR), seems to only affect latched status bits.
 
|Interrupt acknowledge (used by ISR), seems to only affect latched status bits.
 
|-
 
|-
−
|[[:84PCE:Ports:500C|500C]]
+
|500C
 
|00000019
 
|00000019
 
|003FFFFF
 
|003FFFFF
 
|Determines whether bits of [[:84PCE:Ports:5000|5000]] will latch. 0 means raw signal, 1 means latched.
 
|Determines whether bits of [[:84PCE:Ports:5000|5000]] will latch. 0 means raw signal, 1 means latched.
 
|-
 
|-
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|[[:84PCE:Ports:5010|5010]]
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|5010
 
|00000000
 
|00000000
 
|003FFFFF
 
|003FFFFF
 
|Inverts the raw signal of the interrupts corresponding to each 1 bit. Can be used to latch on a high-to-low change.
 
|Inverts the raw signal of the interrupts corresponding to each 1 bit. Can be used to latch on a high-to-low change.
 
|-
 
|-
−
|[[:84PCE:Ports:5014|5014]]
+
|5014
 
|Read-only
 
|Read-only
 
|003FFFFF
 
|003FFFFF
 
|Masked interrupt status (used by ISR). Should be equal to ([[:84PCE:Ports:5000|5000]] & [[:84PCE:Ports:5004|5004]]).
 
|Masked interrupt status (used by ISR). Should be equal to ([[:84PCE:Ports:5000|5000]] & [[:84PCE:Ports:5004|5004]]).
 
|-
 
|-
−
|5018
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|5020
−
|Read-only
+
−
|????????
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−
|''Ports 5018-501F may always read zero''
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−
|-
+
−
|[[:84PCE:Ports:5020|5020]]
+
 
|
 
|
 
|
 
|
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|Ports 5020-503F seem to be identical in function to 5000-501F (but not mirrors). These registers do not seem to actually trigger interrupts. Assuming this chip was meant for use with ARM, this would likely have been intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts.
+
|Ports 5020-503F are identical in function to 5000-501F. These registers do not actually trigger interrupts. Since this IP core was meant for use with ARM, these ports were intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts. However, these ports can be used for other purposes such as reading the state of the ON key.
 +
|-
 +
|5050
 +
|Read-only
 +
|FFFFFFFF
 +
|Revision register. Reads 0x00010900 for revision 1.9.0.
 +
|-
 +
|5054
 +
|Read-only
 +
|FF
 +
|Feature register for input number (IRQ). Reads the number of normal interrupts configured to be handled by the controller, which is 22.
 +
|-
 +
|5055
 +
|Read-only
 +
|FF
 +
|Feature register for input number (FIQ). Reads the number of FIQ interrupts configured to be handled by the controller, which is 22.
 
|-
 
|-
 
|}
 
|}

Latest revision as of 13:47, 16 January 2023

Synopsis

Port Number: 5000-505F

Memory-mapped address: F00000

Function: Interrupt Controller

This port range is used to configure and control interrupts (appears to be model FTINTC010). There are two sets of interrupt control registers, but only the first actually triggers interrupts on the eZ80.

It is arranged in 22-bit bitfields (each occupying a little-endian 32-bit word), with each bit corresponding to a different interrupt source.

Known Sources

Bit    Interrupt Source   
0 ON Button
1 Timer 1
2 Timer 2
3 Timer 3
4 Probably OS timer. Frequency is controlled by bits [1:0] of port 0000.
10 Keyboard
11 LCD Controller
12 Real-Time Clock
13 USB
15 Unknown, but signal seems to be constantly on
16 Added in Python Edition.
18 SPI
19 Added in Python Edition.

Registers

Port    Default    Bits    Information   
5000 Read-Only 003FFFFF Raw interrupt status (can be either raw signal or latched on signal change from low-to-high).
5004 00003011 003FFFFF Interrupt enable mask.
5008 Write-Only 003FFFFF Interrupt acknowledge (used by ISR), seems to only affect latched status bits.
500C 00000019 003FFFFF Determines whether bits of 5000 will latch. 0 means raw signal, 1 means latched.
5010 00000000 003FFFFF Inverts the raw signal of the interrupts corresponding to each 1 bit. Can be used to latch on a high-to-low change.
5014 Read-only 003FFFFF Masked interrupt status (used by ISR). Should be equal to (5000 & 5004).
5020 Ports 5020-503F are identical in function to 5000-501F. These registers do not actually trigger interrupts. Since this IP core was meant for use with ARM, these ports were intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts. However, these ports can be used for other purposes such as reading the state of the ON key.
5050 Read-only FFFFFFFF Revision register. Reads 0x00010900 for revision 1.9.0.
5054 Read-only FF Feature register for input number (IRQ). Reads the number of normal interrupts configured to be handled by the controller, which is 22.
5055 Read-only FF Feature register for input number (FIQ). Reads the number of FIQ interrupts configured to be handled by the controller, which is 22.
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