Difference between revisions of "84PCE:LCD Controller"

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m (→‎36: Memory Data Access Control: Describe RGB/BGR mode more clearly)
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* Pixel clock (CLCP)
 
* Pixel clock (CLCP)
 
* RGB pixel data (CLD)
 
* RGB pixel data (CLD)
−
* Data enable (CLAC)
+
* Data enable (CLAC), only if DE mode is enabled in [[#B1: RGB Interface Control|RGB Interface Control]].
  
−
This is TI's default setting, and causes the scan timing to be completely controlled by the Primecell.
+
RGB Interface with DE mode is TI's default setting, and causes the scan timing to be completely controlled by the Primecell.
  
−
To prevent scan errors, the Primecell must be configured with at least 240 pixel clocks per line and at least 320 lines per frame, plus the back porch values configured in [[#B1: RGB Interface Control|RGB Interface Control]]. Note that these pixel clocks and lines are not required to be during active video of the Primecell, as it drives the pixel clock and line sync pulses even during porches.
+
In DE mode, active video on the Primecell will drive the data enable and RGB pixel data signals, which are accepted by the RGB interface and written to display RAM, if enabled in [[#B0: RAM Control|RAM Control]].
  
−
Active video on the Primecell will drive the data enable and RGB pixel data signals, which are accepted by the RGB interface and written to display RAM, if enabled.
+
In HV mode, the data enable signal is ignored and the porches configured in [[#B1: RGB Interface Control|RGB Interface Control]] are used to determine when pixel data is accepted. To align the pixel data correctly, the RGB interface's configured VSYNC and HSYNC back porches should equal the sum of the Primecell's corresponding Sync Width and Back Porch, and the active video area should be 240x320 pixels. When pixel data is misaligned, pixel clocks outside of the Primecell's active video will write all-zero (black) pixels to display RAM.
  
−
The RGB interface may also be configured with the WO bit of [[#B1: RGB Interface Control|RGB Interface Control]] to bypass display RAM entirely and output the RGB pixel data signals directly to the display. Of course, this requires precisely a 240x320 active video configuration on the Primecell (in CE memory, represented in column-major order).
+
To prevent scan errors, the Primecell must be configured with at least 257 pixel clocks per line (including porches), which allows enough time for the RAM reads starting 17 pixel clocks into each line (see [[#Internal Reads|Internal Reads]]). The datasheet recommends at least 22 pixel clocks of total porch, for at least 262 pixel clocks per line total.
 +
 
 +
In DE mode, active video begins one line after the Primecell first asserts the data enable signal (meaning it begins at the Primecell's second line of active video), so there should be at least 321 lines combined in the Primecell's active video and front porch. In HV mode, the RGB interface VSYNC back porch is configured in [[#B1: RGB Interface Control|RGB Interface Control]], so the Primecell's total number of lines (including porches) should be at least the configured back porch plus 320. If the number of lines is too small, the frame synchronization pulse will be ignored until all 320 lines of active video have been scanned, causing the refresh rate to be halved or more.
 +
 
 +
The RGB interface may also be configured with the WO bit of [[#B1: RGB Interface Control|RGB Interface Control]] to bypass display RAM entirely and output the RGB pixel data signals directly to the display. Of course, this requires a 240x320 active video configuration on the Primecell (in CE memory, represented in column-major order). The datasheet recommends at least 20 pixel clocks of horizontal back porch in this mode, and too small of a back porch can cause scan errors. Additionally, unlike when RAM is used, in DE mode the active video begins on the same line the Primecell asserts the data enable signal. The RM bit of [[#B0: RAM Control|RAM Control]] must still be set for the pixels to be accepted over RGB interface, so it's not possible to use this mode to update display RAM over [[#SPI_Interface|SPI interface]] while displaying a different image over RGB interface.
  
 
== MCU Interface ==
 
== MCU Interface ==
  
−
In this mode, all scan timings are internal. Signals from the RGB interface are ignored, aside from display RAM writes if enabled. Scan timings are determined by [[#B3: Frame Rate Control 1|Frame Rate Control 1]], [[#C6: Frame Rate Control 2|Frame Rate Control 2]], and [[#B2: Porch Setting|Porch Setting]].
+
In this mode, all scan timings are internal. Signals from the RGB interface are ignored, aside from using the pixel clock, RGB pixel data, and data enable signals for display RAM writes if enabled in [[#B0: RAM Control|RAM Control]].
 +
 
 +
Scan timings are determined by [[#B3: Frame Rate Control 1|Frame Rate Control 1]], [[#C6: Frame Rate Control 2|Frame Rate Control 2]], and [[#B2: Porch Setting|Porch Setting]].
 +
 
 +
RGB HV mode cannot reliably be used for display RAM writes in this operating mode, because the active video periods (which determine when to accept pixel data) are not synchronized whatsoever with the RGB interface pixel clock.
  
 
== VSYNC Interface ==
 
== VSYNC Interface ==
  
−
In this mode, all scan timings are internal ''except'' for the frame synchronization pulse. Other signals from the RGB interface are ignored, aside from display RAM writes if enabled.
+
In this mode, all scan timings are internal ''except'' for the frame synchronization pulse. Other signals from the RGB interface are ignored, aside from using the pixel clock, RGB pixel data, and data enable signals for display RAM writes if enabled in [[#B0: RAM Control|RAM Control]].
  
 
This mode allows the frame rate alone to be controlled by the RGB interface, while allowing much more flexibility with the timing of the line configuration, pixel clock, and RAM writes.
 
This mode allows the frame rate alone to be controlled by the RGB interface, while allowing much more flexibility with the timing of the line configuration, pixel clock, and RAM writes.
  
−
Note that if the MCU interface timings are not configured to complete a frame faster than the RGB interface, some frame synchronization pulses will be ignored and the framerate will be effectively halved or more.
+
Note that if the MCU interface timings are not configured to complete a frame faster than the RGB interface, some frame synchronization pulses will be ignored and the framerate will be effectively halved or more. Thus, MCU interface timings should be configured to account for LCD controllers with slower internal clock rate; see [[#C6: Frame Rate Control 2|Frame Rate Control 2]] for information on clock rate variance.
 +
 
 +
RGB HV mode cannot reliably be used for display RAM writes in this operating mode, because the active video periods (which determine when to accept pixel data) are not synchronized whatsoever with the RGB interface pixel clock.
  
 
= RAM access =
 
= RAM access =
Line 59: Line 69:
  
 
Before accessing RAM, a rectangular window should be configured using the [[#2A: Column Address Set|Column Address Set]] and [[#2B: Row Address Set|Row Address Set]] commands. Data is accessed using a Frame Memory Pointer (unique to each interface) which starts at a corner of the configured window and moves in the major (X) direction configured by the [[#36: Memory Data Access Control|Memory Data Access Control]] command. Once the opposite edge of the window is reached, it wraps around and moves the pointer in the minor (Y) direction. Once the opposite ''corner'' of the window has been reached, it either wraps around to the beginning or disallows writes until the Frame Memory Pointer is reset, depending on the WEMODE bits in [[#B0: RAM Control|RAM Control]].
 
Before accessing RAM, a rectangular window should be configured using the [[#2A: Column Address Set|Column Address Set]] and [[#2B: Row Address Set|Row Address Set]] commands. Data is accessed using a Frame Memory Pointer (unique to each interface) which starts at a corner of the configured window and moves in the major (X) direction configured by the [[#36: Memory Data Access Control|Memory Data Access Control]] command. Once the opposite edge of the window is reached, it wraps around and moves the pointer in the minor (Y) direction. Once the opposite ''corner'' of the window has been reached, it either wraps around to the beginning or disallows writes until the Frame Memory Pointer is reset, depending on the WEMODE bits in [[#B0: RAM Control|RAM Control]].
 +
 +
Both the X and Y addresses are represented as 9 bits each; for Frame Memory Pointer values outside of the valid 240x320 or 320x240 range, the row is first masked to 8 bits, and if the pointer is still out of range, the write is ignored. The window end addresses are automatically clamped to the valid range before comparing for equality to the Frame Memory Pointer, so the primary way to cause an out-of-range pointer is to configure a window start address as greater than the corresponding clamped end address.
  
 
TI configures a full-screen row-major window by default (starting in the upper-left corner of the screen, moving left to right across a row, and proceeding through each row from top to bottom). This causes the diagonal screen tearing effect commonly seen on the CE, because each line (column) is only partially updated when scanned to the display.
 
TI configures a full-screen row-major window by default (starting in the upper-left corner of the screen, moving left to right across a row, and proceeding through each row from top to bottom). This causes the diagonal screen tearing effect commonly seen on the CE, because each line (column) is only partially updated when scanned to the display.
Line 85: Line 97:
  
 
RGB666 format (3 bytes per pixel): 1<span style="color: #00f">BBBBBB</span>XX 1<span style="color: #0c0">GGGGGG</span>XX 1<span style="color: #f00">RRRRRR</span>XX
 
RGB666 format (3 bytes per pixel): 1<span style="color: #00f">BBBBBB</span>XX 1<span style="color: #0c0">GGGGGG</span>XX 1<span style="color: #f00">RRRRRR</span>XX
 +
 +
== Internal Reads ==
 +
 +
When scanning the display and RAM bypass is not enabled in [[#B1: RGB Interface Control|RGB Interface Control]], the LCD controller reads each line of its RAM into an internal shift register, which is displayed on the following line. When reading the same pixel currently being written through the RGB or SPI interface, the read safely obtains the old value of the pixel.
 +
 +
The timing for the internal reads is rather unusual, and differs depending on which line of RAM is being read. In all cases, the reads begin 17 pixel clocks after the line synchronization signal, and last for a total of 240 pixel clocks. If the next line synchronization signal occurs before 257 pixel clocks have passed, the shift register's new contents are not used, and the pixels from the previous line are scanned instead.
 +
 +
The internal reads are split into 12-pixel-clock chunks, each of which is responsible for reading 12 pixels. The chunks are processed in increasing address order regardless of the MH bit in [[#36: Memory Data Access Control|Memory Data Access Control]], which instead affects how the shift register is processed. However, the pixels within each chunk are not read in strictly increasing order: 6 pixels are read from the range [0, 120), and 6 pixels are read from the range [120, 240).
 +
 +
For each 12-pixel-clock chunk represented by n in [0, 20), the following tables indicate the pixel clock (offset from 17+n*12) and which pixels in the line are read (offset from n*6).
 +
 +
If the address of the line being read is in [0, 300):
 +
{|-
 +
|<u>Pixel Clock</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Pixels Read</u>
 +
|-
 +
|0
 +
|0, 2, 4, 120, 122, 124
 +
|-
 +
|2
 +
|1, 3, 5, 121, 123, 125
 +
|}
 +
 +
If the address of the line being read is in [300, 320):
 +
{|-
 +
|<u>Pixel Clock</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Pixels Read</u>
 +
|-
 +
|0
 +
|0, 120
 +
|-
 +
|2
 +
|1, 121
 +
|-
 +
|4
 +
|2, 122
 +
|-
 +
|6
 +
|3, 123
 +
|-
 +
|8
 +
|4, 124
 +
|-
 +
|10
 +
|5, 125
 +
|}
  
 
= Command List =
 
= Command List =
Line 275: Line 333:
 
Changes to the scroll area only take effect at the next frame start.
 
Changes to the scroll area only take effect at the next frame start.
  
−
The TFA lines on the left side of the screen are displayed normally, as well as the TBA lines on the right side of the screen. The lines in the middle range [TFA, 320-BFA) participate in horizontal scrolling.
+
The TFA lines on the left side of the screen are displayed normally, as well as the BFA lines on the right side of the screen. The lines in the middle range [TFA, 320-BFA) participate in horizontal scrolling.
  
−
If the ML bit is set in [[#36: Memory Data Access Control|Memory Data Access Control]], the scrolling range is interpreted from right to left, making it [TFA, 320-BFA) under normal line numbering.
+
If the ML bit is set in [[#36: Memory Data Access Control|Memory Data Access Control]], the scrolling range is interpreted from right to left, making it [BFA, 320-TFA) under normal line numbering.
  
 
The datasheet specifies that VSA should hold the number of lines in the scrolling range such that TFA+VSA+BFA=320, but VSA seems to have no effect in practice.
 
The datasheet specifies that VSA should hold the number of lines in the scrolling range such that TFA+VSA+BFA=320, but VSA seems to have no effect in practice.
Line 291: Line 349:
 
|0000h
 
|0000h
 
|N/A
 
|N/A
−
|TFA: Top Fixed Area. Should be between 0 and 320-BFA, inclusive.
+
|TFA: Top Fixed Area. Should be between 0 and 320-BFA, inclusive. If 320 or greater, fills the whole screen.
 
|}
 
|}
  
Line 317: Line 375:
 
|0000h
 
|0000h
 
|N/A
 
|N/A
−
|BFA: Bottom Fixed Area. Should be between 0 and 320-TFA, inclusive.
+
|BFA: Bottom Fixed Area. Should be between 0 and 320-TFA, inclusive. If 320 or greater, this area is disabled.
 
|}
 
|}
  
Line 388: Line 446:
 
If the ML bit is set in [[#36: Memory Data Access Control|Memory Data Access Control]], the line address is interpreted from right to left and VSP is the line to display on the right-hand side, so while VSP=TFA still means no scrolling, increasing the value scrolls the area to the right instead.
 
If the ML bit is set in [[#36: Memory Data Access Control|Memory Data Access Control]], the line address is interpreted from right to left and VSP is the line to display on the right-hand side, so while VSP=TFA still means no scrolling, increasing the value scrolls the area to the right instead.
  
−
The scrolling is designed such that only the lines within the scroll area are rotated; when line 320-BFA is reached in frame memory, the line address returns to TFA. Strictly speaking, the first time in a frame that the line address is ''at least'' 320-BFA, (320-BFA)-TFA is subtracted from the line address. This can be useful knowledge when using the scroll mode for unintended behavior like showing the same lines in multiple parts of the screen.
+
The scrolling is designed such that only the lines within the scroll area are rotated; when line 320-BFA is reached in frame memory, the line address returns to TFA. Strictly speaking, the first time in a frame that the line address is ''greater than'' 319-BFA, (320-BFA)-TFA is subtracted from the line address. This can be useful knowledge when using the scroll mode for unintended behavior like showing the same lines in multiple parts of the screen. Also, if BFA is 320 or larger, the scroll area is located between [TFA, 320) and no wrapping occurs because 319-BFA is treated as a large positive number. If the line address ever remains between 320 and 511 after scroll area wrapping is applied, it attempts to access invalid display RAM addresses and displays garbage, so that should be avoided.
  
 
'''Parameter word 1:'''
 
'''Parameter word 1:'''
Line 421: Line 479:
 
|<u>Description</u>
 
|<u>Description</u>
 
|-
 
|-
−
|3:0
+
|2:0
 
|06h
 
|06h
 
|06h
 
|06h
Line 429: Line 487:
 
* 06h: 18 bits per pixel (RGB666)
 
* 06h: 18 bits per pixel (RGB666)
 
|-
 
|-
−
|7:4
+
|6:4
 
|06h
 
|06h
 
|06h
 
|06h
Line 464: Line 522:
 
* 01h: RGB Interface
 
* 01h: RGB Interface
 
* 02h: VSYNC Interface
 
* 02h: VSYNC Interface
−
* 03h: Reserved
+
* 03h: Reserved. Acts like 00h.
 
|-
 
|-
 
|4
 
|4
Line 556: Line 614:
 
* 00h: MCU interface according to datasheet, seems to act like 02h.
 
* 00h: MCU interface according to datasheet, seems to act like 02h.
 
* 01h: MCU interface according to datasheet, seems to act like 03h.
 
* 01h: MCU interface according to datasheet, seems to act like 03h.
−
* 02h: RGB DE mode. Respects the Data Enable signal for accepting RGB pixel data. This mode should generally be used on the CE.
+
* 02h: RGB DE mode. Respects the Data Enable signal for accepting RGB pixel data and starting active video. This mode should generally be used on the CE.
−
* 03h: RGB HV mode. Accepts RGB pixel data during Horizontal/Vertical active video periods.
+
* 03h: RGB HV mode. Accepts RGB pixel data during active video periods, determined by the HSYNC and VSYNC back porch settings.
 
|-
 
|-
 
|7
 
|7
Line 577: Line 635:
 
|05h
 
|05h
 
|VBP: RGB interface VSYNC back porch. Number of lines, including frame synchronization, to wait before active video.
 
|VBP: RGB interface VSYNC back porch. Number of lines, including frame synchronization, to wait before active video.
−
Seems to be ignored in RGB DE mode, instead waiting for the first line that the Data Enable signal is set.
+
Ignored in RGB DE mode, instead waiting for the first line that the Data Enable signal is set if direct RGB mode is enabled, or the line after otherwise.
 
In RGB HV mode, should be set to VSW+VBP (actual) in the Primecell's LCDTiming1 register.
 
In RGB HV mode, should be set to VSW+VBP (actual) in the Primecell's LCDTiming1 register.
 
|}
 
|}
Line 592: Line 650:
 
|14h
 
|14h
 
|HBP: RGB interface HSYNC back porch. Number of pixels, including line synchronization, to wait before active video.
 
|HBP: RGB interface HSYNC back porch. Number of pixels, including line synchronization, to wait before active video.
−
Seems to be ignored in RGB DE mode, instead waiting for the first pixel that the Data Enable signal is set.
+
Ignored in RGB DE mode, instead waiting for the first pixel that the Data Enable signal is set.
 
In RGB HV mode, should be set to HSW+HBP (actual) in the Primecell's LCDTiming0 register.
 
In RGB HV mode, should be set to HSW+HBP (actual) in the Primecell's LCDTiming0 register.
 
|}
 
|}
Line 683: Line 741:
  
 
The refresh rate can be calculated as 10MHz/divisor/(number of lines)/(250+RTN*16).
 
The refresh rate can be calculated as 10MHz/divisor/(number of lines)/(250+RTN*16).
 +
 +
Note: The base clock rate of 10MHz varies for each calculator. See [[#C6: Frame Rate Control 2|Frame Rate Control 2]] for more details.
  
 
The number of lines depends on the [[#B2: Porch Setting|Porch Setting]], and is equal to (BP+320+FP) in MCU Interface mode and a minimum of (BP+320) in VSYNC Interface mode.
 
The number of lines depends on the [[#B2: Porch Setting|Porch Setting]], and is equal to (BP+320+FP) in MCU Interface mode and a minimum of (BP+320) in VSYNC Interface mode.
Line 721: Line 781:
 
|N/A
 
|N/A
 
|RTNB: Frame rate control for Idle Mode. Affects the duration of each line. See the formula above for how this value is used.
 
|RTNB: Frame rate control for Idle Mode. Affects the duration of each line. See the formula above for how this value is used.
 +
Should be greater than 0, or else the number of pixel clocks per line will be too small for the [[#Internal Reads|Internal Reads]].
 
|-
 
|-
 
|7:5
 
|7:5
Line 741: Line 802:
 
|N/A
 
|N/A
 
|RTNC: Frame rate control for Partial Mode. Affects the duration of each line. See the formula above for how this value is used.
 
|RTNC: Frame rate control for Partial Mode. Affects the duration of each line. See the formula above for how this value is used.
 +
Should be greater than 0, or else the number of pixel clocks per line will be too small for the [[#Internal Reads|Internal Reads]].
 
|-
 
|-
 
|7:5
 
|7:5
Line 959: Line 1,021:
  
 
The refresh rate can be calculated as 10MHz/divisor/(number of lines)/(250+RTNA*16).
 
The refresh rate can be calculated as 10MHz/divisor/(number of lines)/(250+RTNA*16).
 +
 +
Note: The base clock rate of 10MHz varies for each calculator. Some newer datasheets in the ST7789 family indicate a &plusmn;5% variance; clock rates have been [https://cemetech.net/forum/viewtopic.php?t=19674 observed] between 9.85 MHz and 10.28 MHz.
  
 
The divisor is specified in [[#B3: Frame Rate Control 1|Frame Rate Control 1]].
 
The divisor is specified in [[#B3: Frame Rate Control 1|Frame Rate Control 1]].
Line 977: Line 1,041:
 
|0Fh
 
|0Fh
 
|RTNA: Frame rate control for Normal Mode. Affects the duration of each line. See the formula above for how this value is used.
 
|RTNA: Frame rate control for Normal Mode. Affects the duration of each line. See the formula above for how this value is used.
 +
Should be greater than 0, or else the number of pixel clocks per line will be too small for the [[#Internal Reads|Internal Reads]].
 
|-
 
|-
 
|7:5
 
|7:5
Line 1,023: Line 1,088:
 
|02h (6.8V)
 
|02h (6.8V)
 
|AVDD: AVDD setting.
 
|AVDD: AVDD setting.
 +
|}
 +
 +
=== D2: Enable VAP/VAN Signal Output ===
 +
Enables (or disables?) VAP/VAN signal output.
 +
 +
'''Parameter byte 1:'''
 +
{|-
 +
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 +
|<u>HW Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>TI Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Description</u>
 +
|-
 +
|7:0
 +
|00h
 +
|00h
 +
|The datasheet is unclear on this. It only specifies 4Ch as a parameter, but 00h as the default. Presumably writing 4Ch enables and writing 00h disables.
 
|}
 
|}
  
Line 1,531: Line 1,612:
 
|17h (41)
 
|17h (41)
 
|V62N: Voltage for gray level 62 (VN62) is linearly interpolated between VBN and VAN at (64-V62N)/129.
 
|V62N: Voltage for gray level 62 (VN62) is linearly interpolated between VBN and VAN at (64-V62N)/129.
 +
|}
 +
 +
=== E2: Digital Gamma LUT for Red ===
 +
Defines the gamma lookup table for pixels' blue components prior to any BGR swap. The controller enables BGR swap in [[#C0: LCM Control|LCM Control]] by default, so the datasheet names this as the LUT for red, but according to TI's default settings it applies to blue.
 +
 +
When enabled in [[#BA: Digital Gamma Enable|Digital Gamma Enable]], this LUT is used to translate the 6-bit color component to a new 6-bit value, before displaying to the screen with analog gamma.
 +
 +
For some reason, despite the LUT having 64 entries, the least significant bit of the color component input seems to be forced to 0, so only the even-indexed entries of the LUT are ever accessed. As such, it may be most consistent to write the same value to both even and odd entries, and treat them both as if the desired LSB from the EPF setting in [[#B0: RAM Control|RAM Control]] was used as the index.
 +
 +
'''Parameter byte n+1 (n=0 to 63):'''
 +
{|-
 +
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 +
|<u>HW Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>TI Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Description</u>
 +
|-
 +
|7:2
 +
|n
 +
|N/A
 +
|DGM_LUT_Rn: The output mapping when the color component value is equal to n. As mentioned above, when n is odd, the mapping for n-1 is used instead.
 +
|}
 +
 +
=== E3: Digital Gamma LUT for Blue ===
 +
Defines the gamma lookup table for pixels' red components prior to any BGR swap. The controller enables BGR swap in [[#C0: LCM Control|LCM Control]] by default, so the datasheet names this as the LUT for blue, but according to TI's default settings it applies to red.
 +
 +
When enabled in [[#BA: Digital Gamma Enable|Digital Gamma Enable]], this LUT is used to translate the 6-bit color component to a new 6-bit value, before displaying to the screen with analog gamma.
 +
 +
For some reason, despite the LUT having 64 entries, the least significant bit of the color component input seems to be forced to 0, so only the even-indexed entries of the LUT are ever accessed. As such, it may be most consistent to write the same value to both even and odd entries, and treat them both as if the desired LSB from the EPF setting in [[#B0: RAM Control|RAM Control]] was used as the index.
 +
 +
'''Parameter byte n+1 (n=0 to 63):'''
 +
{|-
 +
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 +
|<u>HW Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>TI Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Description</u>
 +
|-
 +
|7:2
 +
|n
 +
|N/A
 +
|DGM_LUT_Bn: The output mapping when the color component value is equal to n. As mentioned above, when n is odd, the mapping for n-1 is used instead.
 +
|}
 +
 +
=== E4: Gate Control ===
 +
Specifies the physical gates (scanlines) used by the LCD, as well as the scan order.
 +
 +
'''Parameter byte 1:'''
 +
{|-
 +
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 +
|<u>HW Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>TI Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Description</u>
 +
|-
 +
|5:0
 +
|27h (320)
 +
|N/A
 +
|NL: The number of physical lines in the display is (NL+1)*8. This should always be set to 320 lines on the CE.
 +
|}
 +
 +
'''Parameter byte 2:'''
 +
{|-
 +
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 +
|<u>HW Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>TI Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Description</u>
 +
|-
 +
|5:0
 +
|00h (0)
 +
|N/A
 +
|SCN: The first physical line in the display is at gate SCN*8. This should always be set to gate 0 on the CE.
 +
|}
 +
 +
'''Parameter byte 3:'''
 +
{|-
 +
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 +
|<u>HW Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>TI Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Description</u>
 +
|-
 +
|0
 +
|0
 +
|N/A
 +
|GS: Gate scan direction. 0 means scan in increasing order (left to right), 1 means scan in decreasing order (right to left).
 +
Setting to 1 effectively reverses the display output horizontally. The exact set of gates which are scanned when reversed depends on the TMG bit below.
 +
|-
 +
|1
 +
|0
 +
|N/A
 +
|SS: Source scan direction. 0 means scan in increasing order (top to bottom), 1 means scan in decreasing order (bottom to top).
 +
Setting to 1 effectively reverses the display output vertically. However, the RGB subpixels are not reversed.
 +
Note: This bit is undocumented, always set as 0 in the datasheet.
 +
|-
 +
|2
 +
|0
 +
|N/A
 +
|SM: Interlaced scan mode. 0 means scan normally, 1 means scan all even lines first, followed by all odd lines.
 +
The pixel data used for the scan is not changed, meaning the first half (normally on the left) is scanned on the even lines and the second half (normally on the right) is scanned on the odd lines.
 +
|-
 +
|4
 +
|1
 +
|N/A
 +
|TMG: Gate mirror selection. When GS=1, 0 means local mirror across the active gates specified in NL and SCN, and 1 means full mirror across all 320 gates.
 +
In other words, for local mirror, gates [SCN, SCN+NL) are always used, and for full mirror, gates [SCN, SCN+NL) or [320-(SCN+NL), 320-SCN) are used depending on the GS setting.
 +
|}
 +
 +
=== E9: Equalize Time Control ===
 +
Specifies equalize and pre-drive times.
 +
 +
'''Parameter byte 1:'''
 +
{|-
 +
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 +
|<u>HW Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>TI Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Description</u>
 +
|-
 +
|4:0
 +
|11h
 +
|08h
 +
|SEQ: Source equalize time is SEQ*4 full pixel durations. Minimum value is 1.
 +
|}
 +
 +
'''Parameter byte 2:'''
 +
{|-
 +
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 +
|<u>HW Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>TI Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Description</u>
 +
|-
 +
|-
 +
|4:0
 +
|11h
 +
|08h
 +
|SPRET: Source pre-drive time is SPRET*4 full pixel durations. Minimum value is 1.
 +
|}
 +
 +
'''Parameter byte 3:'''
 +
{|-
 +
|<u>Bit</u>&nbsp;&nbsp;&nbsp;
 +
|<u>HW Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>TI Default</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Description</u>
 +
|-
 +
|-
 +
|3:0
 +
|08h
 +
|08h
 +
|GEQ: Gate equalize time is GEQ*4 full pixel durations.
 
|}
 
|}

Latest revision as of 12:59, 13 June 2024

The CE contains two LCD controllers which work in tandem. This page primarily focuses on the one directly driving the LCD, the Sitronix ST7789.

See also the Primecell PL111 which drives the RGB interface, and the SPI Controller which provides the command interface.

Contents

Quick Specs

  • Sitronix ST7789 family LCD controller
  • TFT color LCD
  • Supports RGB and SPI interfaces
  • 172,800 bytes internal RAM
  • 76,800 pixels (240x320 resolution)
  • Power-saving 8-color mode
  • 262,144 = 2^18 = 6x6x6 colors
  • Data sheet: https://www.rhydolabz.com/documents/33/ST7789.pdf
  • Physical LCD:

Overview

The LCD is a 240x320 pixel display rotated 90 degrees. To make terminology consistent, directions will be described relative to the CE itself, not relative to the display. As such, each scanline appears in a vertical orientation and the display is scanned from left to right. Note that the datasheet will not agree with this page when it comes to the terms "row" and "column". When appropriate, columns (which correspond to scanlines) will be referred to as "lines" to be more consistent with the datasheet.

Operating modes

The controller operates in one of three modes, dictating the refresh rate and scan timing:

RGB Interface

In this mode, the controller accepts the following signals from the Primecell PL111:

  • Frame synchronization pulse (CLFP)
  • Line synchronization pulse (CLLP)
  • Pixel clock (CLCP)
  • RGB pixel data (CLD)
  • Data enable (CLAC), only if DE mode is enabled in RGB Interface Control.

RGB Interface with DE mode is TI's default setting, and causes the scan timing to be completely controlled by the Primecell.

In DE mode, active video on the Primecell will drive the data enable and RGB pixel data signals, which are accepted by the RGB interface and written to display RAM, if enabled in RAM Control.

In HV mode, the data enable signal is ignored and the porches configured in RGB Interface Control are used to determine when pixel data is accepted. To align the pixel data correctly, the RGB interface's configured VSYNC and HSYNC back porches should equal the sum of the Primecell's corresponding Sync Width and Back Porch, and the active video area should be 240x320 pixels. When pixel data is misaligned, pixel clocks outside of the Primecell's active video will write all-zero (black) pixels to display RAM.

To prevent scan errors, the Primecell must be configured with at least 257 pixel clocks per line (including porches), which allows enough time for the RAM reads starting 17 pixel clocks into each line (see Internal Reads). The datasheet recommends at least 22 pixel clocks of total porch, for at least 262 pixel clocks per line total.

In DE mode, active video begins one line after the Primecell first asserts the data enable signal (meaning it begins at the Primecell's second line of active video), so there should be at least 321 lines combined in the Primecell's active video and front porch. In HV mode, the RGB interface VSYNC back porch is configured in RGB Interface Control, so the Primecell's total number of lines (including porches) should be at least the configured back porch plus 320. If the number of lines is too small, the frame synchronization pulse will be ignored until all 320 lines of active video have been scanned, causing the refresh rate to be halved or more.

The RGB interface may also be configured with the WO bit of RGB Interface Control to bypass display RAM entirely and output the RGB pixel data signals directly to the display. Of course, this requires a 240x320 active video configuration on the Primecell (in CE memory, represented in column-major order). The datasheet recommends at least 20 pixel clocks of horizontal back porch in this mode, and too small of a back porch can cause scan errors. Additionally, unlike when RAM is used, in DE mode the active video begins on the same line the Primecell asserts the data enable signal. The RM bit of RAM Control must still be set for the pixels to be accepted over RGB interface, so it's not possible to use this mode to update display RAM over SPI interface while displaying a different image over RGB interface.

MCU Interface

In this mode, all scan timings are internal. Signals from the RGB interface are ignored, aside from using the pixel clock, RGB pixel data, and data enable signals for display RAM writes if enabled in RAM Control.

Scan timings are determined by Frame Rate Control 1, Frame Rate Control 2, and Porch Setting.

RGB HV mode cannot reliably be used for display RAM writes in this operating mode, because the active video periods (which determine when to accept pixel data) are not synchronized whatsoever with the RGB interface pixel clock.

VSYNC Interface

In this mode, all scan timings are internal except for the frame synchronization pulse. Other signals from the RGB interface are ignored, aside from using the pixel clock, RGB pixel data, and data enable signals for display RAM writes if enabled in RAM Control.

This mode allows the frame rate alone to be controlled by the RGB interface, while allowing much more flexibility with the timing of the line configuration, pixel clock, and RAM writes.

Note that if the MCU interface timings are not configured to complete a frame faster than the RGB interface, some frame synchronization pulses will be ignored and the framerate will be effectively halved or more. Thus, MCU interface timings should be configured to account for LCD controllers with slower internal clock rate; see Frame Rate Control 2 for information on clock rate variance.

RGB HV mode cannot reliably be used for display RAM writes in this operating mode, because the active video periods (which determine when to accept pixel data) are not synchronized whatsoever with the RGB interface pixel clock.

RAM access

Access to the display RAM is provided to both the RGB and SPI interfaces. Which interface is currently given access is determined by the RM bit of RAM Control, and the data format for each interface is determined by Interface Pixel Format.

Before accessing RAM, a rectangular window should be configured using the Column Address Set and Row Address Set commands. Data is accessed using a Frame Memory Pointer (unique to each interface) which starts at a corner of the configured window and moves in the major (X) direction configured by the Memory Data Access Control command. Once the opposite edge of the window is reached, it wraps around and moves the pointer in the minor (Y) direction. Once the opposite corner of the window has been reached, it either wraps around to the beginning or disallows writes until the Frame Memory Pointer is reset, depending on the WEMODE bits in RAM Control.

Both the X and Y addresses are represented as 9 bits each; for Frame Memory Pointer values outside of the valid 240x320 or 320x240 range, the row is first masked to 8 bits, and if the pointer is still out of range, the write is ignored. The window end addresses are automatically clamped to the valid range before comparing for equality to the Frame Memory Pointer, so the primary way to cause an out-of-range pointer is to configure a window start address as greater than the corresponding clamped end address.

TI configures a full-screen row-major window by default (starting in the upper-left corner of the screen, moving left to right across a row, and proceeding through each row from top to bottom). This causes the diagonal screen tearing effect commonly seen on the CE, because each line (column) is only partially updated when scanned to the display.

RGB Interface

Each pixel output by the Primecell PL111 is sent over the RGB interface and written to display RAM, if access is enabled. This method has the most performance, and allows using Primecell features such as DMA and color palettes.

If both the RM and WEMODE1 bits of RAM Control are 1, the frame synchronization pulse resets the Frame Memory Pointer to the start of the configured window, similar to the Write Memory command. Additionally, regardless of the WEMODE1 bit, the Frame Memory Pointer is reset when changing the RM bit from 0 to 1, which can be useful when the window is changed after frame synchronization and before active video.

On the CE, an RGB565 data signal is connected to the RGB666 interface by duplicating the MSB of the red and blue components to the LSB of each. If the RGB interface color format is set to 18bpp, this color is written directly to display RAM. On the other hand, if set to 16bpp, the interface interprets the original RGB565 signal and generates the LSBs of red and blue based on the EPF field of RAM Control.

Note: The Primecell's 12bpp mode outputs an RGB444 data signal, but the RGB interface doesn't support a 12bpp color format for some reason, so it's effectively expanded to RGB565 first with the unspecified bits as 0: RRRR0GGGG00BBBB0

SPI Interface

Pixels can also be sent over the SPI command interface if access is enabled. It has rather slow throughput, but is the only way to write full 18bpp data, or reconfigure the window independently of frame timing. Pixel writes are initiated by the Write Memory or Write Memory Continue commands, and pixels are written as a sequence of parameter bytes. Only fully specified pixels are written to the display RAM, not individual components.

The SPI interface supports RGB444, RGB565, and RGB666 formats. The first two are expanded to RGB666 based on the EPF field of RAM Control.

Note: Each parameter byte is 9 bits in the SPI protocol, including the leading 1 bit indicating a parameter. X bits are ignored. The red and blue fields here are swapped relative to the datasheet, because the datasheet was written assuming a default BGR swap setting enabled in LCM Control.

RGB444 format (1.5 bytes per pixel): 1BBBBGGGG 1RRRRBBBB 1GGGGRRRR

RGB565 format (2 bytes per pixel): 1BBBBBGGG 1GGGRRRRR (or bytes swapped if the ENDIAN bit of RAM Control is 1)

RGB666 format (3 bytes per pixel): 1BBBBBBXX 1GGGGGGXX 1RRRRRRXX

Internal Reads

When scanning the display and RAM bypass is not enabled in RGB Interface Control, the LCD controller reads each line of its RAM into an internal shift register, which is displayed on the following line. When reading the same pixel currently being written through the RGB or SPI interface, the read safely obtains the old value of the pixel.

The timing for the internal reads is rather unusual, and differs depending on which line of RAM is being read. In all cases, the reads begin 17 pixel clocks after the line synchronization signal, and last for a total of 240 pixel clocks. If the next line synchronization signal occurs before 257 pixel clocks have passed, the shift register's new contents are not used, and the pixels from the previous line are scanned instead.

The internal reads are split into 12-pixel-clock chunks, each of which is responsible for reading 12 pixels. The chunks are processed in increasing address order regardless of the MH bit in Memory Data Access Control, which instead affects how the shift register is processed. However, the pixels within each chunk are not read in strictly increasing order: 6 pixels are read from the range [0, 120), and 6 pixels are read from the range [120, 240).

For each 12-pixel-clock chunk represented by n in [0, 20), the following tables indicate the pixel clock (offset from 17+n*12) and which pixels in the line are read (offset from n*6).

If the address of the line being read is in [0, 300):

Pixel Clock    Pixels Read
0 0, 2, 4, 120, 122, 124
2 1, 3, 5, 121, 123, 125

If the address of the line being read is in [300, 320):

Pixel Clock    Pixels Read
0 0, 120
2 1, 121
4 2, 122
6 3, 123
8 4, 124
10 5, 125

Command List

This is the list of commands usable via the SPI Controller. All command IDs are listed in hexadecimal.

The SPI transfer format is 9 bits per byte. The first 9-bit transfer of every command is a 0 bit followed by the command ID byte, and each following transfer is a 1 bit followed by a parameter byte.

All 16-bit parameters are two byte transfers in big-endian order, except for pixel parameters depending on configuration. Unless otherwise specified, unused bits in parameters should be set to 0.

It's allowed to send fewer parameter bytes than the maximum the command takes; each parameter byte is immediately applied as it's received. A partial byte transfer can be cancelled safely by disabling the chip select signal (bit 0 of CR2 on the SPI controller).

Read commands don't seem to work properly on CE hardware, so they aren't described here. Additionally, commands not applicable to the CE because of no connected signals (Tear Effect, Brightness Control, Non-Volatile Memory) are not documented. Voltage-related commands will only be listed in order to document TI's configured values.

Command Table 1

00: No Operation

Takes no parameters and does nothing. It can be used to leave the controller in a state where an accidentally sent parameter has no effect.

01: Software Reset

Resets most parameters to their factory default values, and enters both Sleep mode and Display Off mode. Must wait 5ms before sending another command, or 120ms if initiated in Sleep mode.

Display RAM is unaffected by this operation, as well as the Memory Data Access Control and Interface Pixel Format parameters.

10: Sleep In

Enters Sleep mode. Must wait 5ms before sending another command.

11: Sleep Out

Exits Sleep mode. Must wait 5ms before sending another command. Must wait 120ms before entering Sleep mode again.

12: Partial Display Mode On

Enables Partial Display mode on the next frame. See Partial Area and Partial Control.

As a side effect, this resets the Vertical Scroll Start Address to zero.

Optionally uses a different refresh rate in MCU or VSYNC interface modes, according to Frame Rate Control 1 and Porch Setting.

13: Normal Display Mode On

Disables Partial Display mode and Vertical Scroll mode on the next frame.

As a side effect, this resets the Vertical Scroll Start Address to zero.

20: Display Inversion Off

Disables display inversion immediately. This may require frame synchronization to avoid tearing.

If the XINV bit is set in LCM Control, this command enables display inversion instead.

21: Display Inversion On

Enables display inversion immediately. This may require frame synchronization to avoid tearing.

If the XINV bit is set in LCM Control, this command disables display inversion instead.

26: Gamma Set

Applies a gamma preset.

Parameter byte 1:

Bit    HW Default    TI Default    Description
3:0 01h 02h GC: Gamma curve. Invalid values default to 01h.
  • 01h: G2.2
  • 02h: G1.8
  • 04h: G2.5
  • 08h: G1.0

28: Display Off

Enables Display Off mode on the next frame. This mode's only effect is forcing all-white frames to be output.

29: Display On

Disables Display Off mode on the next frame.

2A: Column Address Set

Sets the X address range for the memory access window.

The X dimension is always the "major" dimension of the window, depending on the MV bit in Memory Data Access Control. In other words, the Frame Memory Pointer always moves in the X dimension first. The selected dimension also determines whether the maximum value is 239 or 319.

The Address Order configured on the X dimension determines the edge of the display RAM referred to by the 0 address. The X value effectively always increases as it moves through the range, thus the range should always be configured with XS≤XE.

Parameter word 1:

Bit    HW Default    TI Default    Description
8:0 0000h 0000h XS: X Start Address. Should be between 0 and XE, inclusive.

Parameter word 2:

Bit    HW Default    TI Default    Description
8:0 00EFh 013Fh XE: X End Address. Should be between XS and 239 or 319, inclusive.

2B: Row Address Set

Sets the Y address range for the memory access window.

The Y dimension is always the "minor" dimension of the window, depending on the MV bit in Memory Data Access Control. In other words, the Frame Memory Pointer always moves in the Y dimension second. The selected dimension also determines whether the maximum value is 239 or 319.

The Address Order configured on the Y dimension determines the edge of the display RAM referred to by the 0 address. The Y value effectively always increases as it moves through the range, thus the range should always be configured with YS≤YE.

Parameter word 1:

Bit    HW Default    TI Default    Description
8:0 0000h 0000h YS: Y Start Address. Should be between 0 and YE, inclusive.

Parameter word 2:

Bit    HW Default    TI Default    Description
8:0 013Fh 00EFh YE: Y End Address. Should be between YS and 239 or 319, inclusive.

2C: Write Memory

All parameters to this command are written to display RAM in order. See RAM Access.

Before the first pixel is written, resets the Frame Memory Pointer to (XS, YS) as specified in the Column Address Set and Row Address Set commands. If no pixels are written, the Frame Memory Pointer is not reset.

30: Partial Area

Sets the display line range for Partial Mode.

Changes to the partial area only take effect at the next frame start.

Lines inside the inclusive range [PSL, PEL] are displayed normally, and lines outside the range are displayed in a solid white or black depending on the NDL bit in Partial Control.

If PSL>PEL, then the two inclusive ranges [0, PEL] and [PSL, 319] are displayed normally, while the exclusive range (PEL, PSL) is displayed in solid white or black.

If the ML bit is set in Memory Data Access Control, line 0 refers to the right edge of the display, and line numbers increase to the left.

Parameter word 1:

Bit    HW Default    TI Default    Description
8:0 0000h N/A PSL: Partial Start Line. Should be between 0 and 319, inclusive.

Parameter word 2:

Bit    HW Default    TI Default    Description
8:0 013Fh N/A PEL: Partial End Line. Should be between 0 and 319, inclusive.

33: Vertical Scrolling Definition

Sets the display line range for Vertical Scroll mode. Note since the display is rotated, this is actually a horizontal scroll mode.

Changes to the scroll area only take effect at the next frame start.

The TFA lines on the left side of the screen are displayed normally, as well as the BFA lines on the right side of the screen. The lines in the middle range [TFA, 320-BFA) participate in horizontal scrolling.

If the ML bit is set in Memory Data Access Control, the scrolling range is interpreted from right to left, making it [BFA, 320-TFA) under normal line numbering.

The datasheet specifies that VSA should hold the number of lines in the scrolling range such that TFA+VSA+BFA=320, but VSA seems to have no effect in practice.

Parameter word 1:

Bit    HW Default    TI Default    Description
8:0 0000h N/A TFA: Top Fixed Area. Should be between 0 and 320-BFA, inclusive. If 320 or greater, fills the whole screen.

Parameter word 2:

Bit    HW Default    TI Default    Description
8:0 0140h N/A VSA: Vertical Scrolling Area. Seems to be ignored, but recommended to set to 320-(TFA+BFA).

Parameter word 3:

Bit    HW Default    TI Default    Description
8:0 0000h N/A BFA: Bottom Fixed Area. Should be between 0 and 320-TFA, inclusive. If 320 or greater, this area is disabled.

36: Memory Data Access Control

Determines the behavior of the Frame Memory Pointer, display scan order, and RGB/BGR output.

Note: Most bits in this register can be inverted by bits in LCM Control.

Parameter byte 1:

Bit    HW Default    TI Default    Description
2 0 0 MH: Display data latch order. 0 means scan each line from top to bottom, 1 means from bottom to top.

This does not change the order of the display pixels unless in RGB Interface RAM bypass mode. Can be inverted by the XMH bit in LCM Control.

3 0 1 RGB: RGB/BGR order. 0 means normal RGB output, 1 means the red and blue components are swapped.

Can be inverted by the XBGR bit in LCM Control. Important: TI-OS inverts this bit by default!

4 0 0 ML: Line address order. 0 means scan the frame from left to right, 1 means from right to left.

This does not change the order of the displayed pixels unless in RGB Interface RAM bypass mode. Some features are affected by line address order, see Partial Area and Vertical Scrolling Definition.

5 0 0 MV: Page/column order. 0 means X address moves vertically and Y address moves horizontally, 1 means X address moves horizontally and Y address moves vertically.

Can be inverted by the XMV bit in LCM Control. Important: TI-OS inverts this bit by default!

Changing this before a Write Memory Continue effectively swaps the absolute horizontal and vertical coordinates of the Frame Memory Pointer.

6 0 0 MX: Column address order. 0 means addresses increase from top to bottom, 1 means addresses increase from bottom to top.

Can be inverted by the XMX bit in LCM Control.

Changing this before a Write Memory Continue leaves the Frame Memory Pointer at the same absolute pixel, meaning the X or Y address is subtracted from 239 in the new coordinate system.

7 0 0 MY: Page address order. 0 means addresses increase from left to right, 1 means addresses increase from right to left.

Can be inverted by the XMY bit in LCM Control.

Changing this before a Write Memory Continue leaves the Frame Memory Pointer at the same absolute pixel, meaning the X or Y address is subtracted from 319 in the new coordinate system.

37: Vertical Scroll Start Address

Sets the starting line address in frame memory to be displayed in the scroll area in Vertical Scroll mode. Note since the display is rotated, this is actually a horizontal scroll mode.

Changes to the scroll address only take effect at the next frame start.

See Vertical Scrolling Definition to set up the scroll area.

VSP is set to the line to display on the left-hand side of the scroll area between [TFA, 320-BFA). This means setting VSP=TFA means no scrolling, and increasing the value scrolls the area to the left.

If the ML bit is set in Memory Data Access Control, the line address is interpreted from right to left and VSP is the line to display on the right-hand side, so while VSP=TFA still means no scrolling, increasing the value scrolls the area to the right instead.

The scrolling is designed such that only the lines within the scroll area are rotated; when line 320-BFA is reached in frame memory, the line address returns to TFA. Strictly speaking, the first time in a frame that the line address is greater than 319-BFA, (320-BFA)-TFA is subtracted from the line address. This can be useful knowledge when using the scroll mode for unintended behavior like showing the same lines in multiple parts of the screen. Also, if BFA is 320 or larger, the scroll area is located between [TFA, 320) and no wrapping occurs because 319-BFA is treated as a large positive number. If the line address ever remains between 320 and 511 after scroll area wrapping is applied, it attempts to access invalid display RAM addresses and displays garbage, so that should be avoided.

Parameter word 1:

Bit    HW Default    TI Default    Description
8:0 0000h N/A VSP: Vertical Scroll Pointer. Should be between [TFA, 320-BFA), but can be set outside that range for other effects.

38: Idle Mode Off

Disables Idle Mode on the next frame, allowing full range of color display.

39: Idle Mode On

Enables Idle Mode on the next frame, displaying 8 colors based on the most significant bit of each color component.

Optionally uses a different refresh rate in MCU or VSYNC interface modes, according to Frame Rate Control 1 and Porch Setting.

3A: Interface Pixel Format

Specifies the pixel format accepted through the RGB and SPI interfaces. See RAM Access.

Parameter byte 1:

Bit    HW Default    TI Default    Description
2:0 06h 06h SPI interface color format. Invalid values default to 06h.
  • 03h: 12 bits per pixel (RGB444)
  • 05h: 16 bits per pixel (RGB565)
  • 06h: 18 bits per pixel (RGB666)
6:4 06h 06h RGB interface color format. Invalid values default to 06h.
  • 05h: 16 bits per pixel (RGB565)
  • 06h: 18 bits per pixel (RGB666)

3C: Write Memory Continue

All parameters to this command are written to display RAM in order. See RAM Access.

The Frame Memory Pointer resumes from the location following the last pixel written in a Write Memory or Write Memory Continue command. This location is not affected by memory writes through the RGB interface.

Note: This command is buggy when the first written pixel's X address is equal to the X End Address in Column Address Set. When the Y address is updated during the wrap-around to the X Start Address, the pixel at the X End Address is written to the new Y address instead of the old one. Additionally, if the WEMODE0 bit of RAM Control is 0 and the end of the window is reached, the pixel fails to be written at all. To avoid this bug, write multiple pixels in the same Write Memory Continue command and ensure the wrap-around does not occur on the first pixel.

Command Table 2

B0: RAM Control

Specifies the operating mode and parameters for the RAM Access interface.

Parameter byte 1:

Bit    HW Default    TI Default    Description
1:0 00h 01h DM: Display operating mode. See Operating modes.

Changes to the mode apply on the next frame start. If the previous mode was MCU or VSYNC, it waits until after the front porch of the current frame.

  • 00h: MCU Interface
  • 01h: RGB Interface
  • 02h: VSYNC Interface
  • 03h: Reserved. Acts like 00h.
4 0 1 RM: RAM access selection. 0 means access from the SPI interface, 1 means access from the RGB interface.

Parameter byte 2:

Bit    HW Default    TI Default    Description
1:0 00h 00h MDT: Method of data transfer. Not applicable to the SPI interface on the CE.
2 0 0 RIM: RGB interface bus width. 0 means 18-bit, 1 means 6-bit. This should be set to 18-bit on the CE.
3 0 0 ENDIAN: Specifies byte endianness of RGB565 pixels over the SPI interface. 0 means big-endian, 1 means little-endian.
5:4 03h 03h EPF: Expanded pixel format. Specifies how the least significant bits of color components should be set in RGB444 and RGB565 modes.
  • 00h: Set LSBs to 0.
  • 01h: Set LSBs to 1.
  • 02h: Set LSBs to the MSBs of the same color component. In RGB444 mode, the upper 2 bits are copied.
  • 03h: Set LSBs to the LSB of the green component. In RGB444 mode, acts like 02h.
6 1 1 WEMODE0: Wrap at end mode for SPI interface. 1 means wrap back to the start of the output window, 0 means disallow writes until the Frame Memory Pointer is reset.

Note: This bit is undocumented, always set as 1 in the datasheet.

7 1 1 WEMODE1: Wrap at end mode for RGB interface. 1 means disallow writes until the Frame Memory Pointer is reset, 0 means wrap back to the start of the output window. When set to 0, frame synchronization signals will not reset the Frame Memory Pointer.

Note: This bit is undocumented, always set as 1 in the datasheet.

B1: RGB Interface Control

Controls parameters for the RGB Interface operating mode. See also the Primecell PL111's timing registers.

Parameter byte 1:

Bit    HW Default    TI Default    Description
0 0 1 EPL: ENABLE polarity. 0 means RGB pixel data is accepted when Data Enable signal is high, 1 means low.

This should match the IOE bit in the Primecell's LCDTiming2 register.

1 0 0 DPL: DOTCLK polarity. 0 means RGB data is sampled on the rising edge of the pixel clock, 1 means falling edge.

This should be the inverse of the IPC bit in the Primecell's LCDTiming2 register.

2 0 0 HSPL: HSYNC polarity. 0 means the line synchronization signal is low active, 1 means high active.

This should be the inverse of the IHS bit in the Primecell's LCDTiming2 register.

3 0 0 VSPL: VSYNC polarity. 0 means the frame synchronization signal is low active, 1 means high active.

This should be the inverse of the IVS bit in the Primecell's LCDTiming2 register.

6:5 02h 00h RCM: RGB interface Data Enable mode.
  • 00h: MCU interface according to datasheet, seems to act like 02h.
  • 01h: MCU interface according to datasheet, seems to act like 03h.
  • 02h: RGB DE mode. Respects the Data Enable signal for accepting RGB pixel data and starting active video. This mode should generally be used on the CE.
  • 03h: RGB HV mode. Accepts RGB pixel data during active video periods, determined by the HSYNC and VSYNC back porch settings.
7 0 0 WO: Direct RGB mode. 0 means write RGB pixel data to display RAM, 1 means bypass RAM and send RGB pixel data directly to the display.

Note: In direct RGB mode, the RM bit in RAM Control must be set to 1, despite display RAM being bypassed.

Parameter byte 2:

Bit    HW Default    TI Default    Description
6:0 02h 05h VBP: RGB interface VSYNC back porch. Number of lines, including frame synchronization, to wait before active video.

Ignored in RGB DE mode, instead waiting for the first line that the Data Enable signal is set if direct RGB mode is enabled, or the line after otherwise. In RGB HV mode, should be set to VSW+VBP (actual) in the Primecell's LCDTiming1 register.

Parameter byte 3:

Bit    HW Default    TI Default    Description
4:0 14h 14h HBP: RGB interface HSYNC back porch. Number of pixels, including line synchronization, to wait before active video.

Ignored in RGB DE mode, instead waiting for the first pixel that the Data Enable signal is set. In RGB HV mode, should be set to HSW+HBP (actual) in the Primecell's LCDTiming0 register.

B2: Porch Setting

Sets porch durations for the MCU Interface and VSYNC Interface operating modes.

Optionally allows enabling separate porch durations for Idle Mode and Partial Mode. If both modes are active, Partial Mode's settings take priority.

Parameter byte 1:

Bit    HW Default    TI Default    Description
6:0 0Ch 0Ch BPA: Back porch duration in Normal Mode. Number of lines, including frame synchronization, to wait before active video. Must be at least 1.

Parameter byte 2:

Bit    HW Default    TI Default    Description
6:0 0Ch 0Ch FPA: Front porch duration in Normal Mode. Number of lines after active video to wait for the next frame. Must be at least 1.

Ignored in VSYNC Interface operating mode, where the front porch lasts until the next frame synchronization signal.

Parameter byte 3:

Bit    HW Default    TI Default    Description
0 0 0 PSEN: Separate porch control enable. 1 means the following parameters are applied, 0 means Idle Mode and Partial Mode use Normal Mode's parameters.

Parameter byte 4:

Bit    HW Default    TI Default    Description
3:0 03h 03h BPB: Back porch duration in Idle Mode. Number of lines (divided by 4), including frame synchronization, to wait before active video. Must be at least 1.
7:4 03h 03h FPB: Front porch duration in Idle Mode. Number of lines (divided by 4) after active video to wait for the next frame. Must be at least 1.

Ignored in VSYNC Interface operating mode, where the front porch lasts until the next frame synchronization signal.

Parameter byte 5:

Bit    HW Default    TI Default    Description
3:0 03h 03h BPC: Back porch duration in Partial Mode. Number of lines (divided by 4), including frame synchronization, to wait before active video. Must be at least 1.
7:4 03h 03h FPC: Front porch duration in Partial Mode. Number of lines (divided by 4) after active video to wait for the next frame. Must be at least 1.

Ignored in VSYNC Interface operating mode, where the front porch lasts until the next frame synchronization signal.

B3: Frame Rate Control 1

Controls the frame rate for Idle Mode and Partial Mode while in the MCU Interface or VSYNC Interface operating modes.

The refresh rate can be calculated as 10MHz/divisor/(number of lines)/(250+RTN*16).

Note: The base clock rate of 10MHz varies for each calculator. See Frame Rate Control 2 for more details.

The number of lines depends on the Porch Setting, and is equal to (BP+320+FP) in MCU Interface mode and a minimum of (BP+320) in VSYNC Interface mode.

If both Idle Mode and Partial Mode are active, Partial Mode's settings take priority.

Parameter byte 1:

Bit    HW Default    TI Default    Description
1:0 00h N/A DIV: Frame rate divisor. Divides the base clock frequency of 10MHz, even in Normal Mode.
  • 00h: Divide by 1
  • 01h: Divide by 2
  • 10h: Divide by 4
  • 11h: Divide by 8
4 0 N/A FRSEN: Separate frame rate control enable. 1 means the parameters of this command are applied, 0 means Idle Mode and Partial Mode use Frame Rate Control 2.

Parameter byte 2:

Bit    HW Default    TI Default    Description
4:0 0Fh N/A RTNB: Frame rate control for Idle Mode. Affects the duration of each line. See the formula above for how this value is used.

Should be greater than 0, or else the number of pixel clocks per line will be too small for the Internal Reads.

7:5 00h N/A NLB: Polarity inversion method in Idle Mode.
  • 00h: Dot inversion
  • 07h: Line inversion

Parameter byte 3:

Bit    HW Default    TI Default    Description
4:0 0Fh N/A RTNC: Frame rate control for Partial Mode. Affects the duration of each line. See the formula above for how this value is used.

Should be greater than 0, or else the number of pixel clocks per line will be too small for the Internal Reads.

7:5 00h N/A NLC: Polarity inversion method in Partial Mode.
  • 00h: Dot inversion
  • 07h: Line inversion

B5: Partial Control

Controls the specifics of Partial Mode scan behavior.

Parameter byte 1:

Bit    HW Default    TI Default    Description
3:0 00h N/A ISC: Interval scan cycle length. The number of frames between scans of the non-display area is ISC*2+1.

This field has no effect if PTGISC=0.

4 0 N/A PTGISC: Interval scan enable. 1 means non-display area uses interval scan, 0 means normal scan.
7 0 N/A NDL: Non-display level. Controls the gray level of the non-display area, 0 means white and 1 means black.

B7: Gate Control

Voltage levels for gates.

Parameter byte 1:

Bit    HW Default    TI Default    Description
2:0 05h (-10.43V) 05h (-10.43V) VGLS: VGL setting.
6:4 03h (13.26V) 03h (13.26V) VGHS: VGH setting.

BA: Digital Gamma Enable

Enables or disables the Digital Gamma feature.

When enabled, the Digital Gamma LUT for Red and Digital Gamma LUT for Blue are used to remap red and blue color components before applying analog gamma.

Parameter byte 1:

Bit    HW Default    TI Default    Description
2 0 N/A DGMEN: Digital gamma enable. 1 means enabled, 0 means disabled.

BB: VCOM Setting

Voltage level for VCOM.

Parameter byte 1:

Bit    HW Default    TI Default    Description
5:0 20h (0.9V) 17h (0.675V) VCOMS: VCOM setting.

C0: LCM Control

Allows inverting bits of various display parameters via XOR.

Parameter byte 1:

Bit    HW Default    TI Default    Description
0 0 0 XGS: When set to 1, inverts the GS bit of Gate Control, aka gate scan direction.
1 0 1 XMV: When set to 1, inverts the MV bit of Memory Data Access Control, aka page/column order.
2 1 0 XMH: When set to 1, inverts the MH bit of Memory Data Access Control, aka display data latch order.
3 1 0 XMX: When set to 1, inverts the MX bit of Memory Data Access Control, aka column address order.
4 0 0 XINV: When set to 1, inverts the effect of the Display Inversion On and Display Inversion Off commands.
5 1 1 XBGR: When set to 1, inverts the RGB bit of Memory Data Access Control, aka RGB/BGR order.
6 0 0 XMY: When set to 1, inverts the MY bit of Memory Data Access Control, aka page address order.

C2: VDV and VRH Command Enable

Enables or disables the VRH Set and VDV Set commands.

Parameter byte 1:

Bit    HW Default    TI Default    Description
0 1 1 CMDEN: VDV and VRH command write enable. 1 means the command parameters are used, 0 means settings from NVM are used.

Parameter byte 2:

Bit    HW Default    TI Default    Description
7:0 FFh N/A This field should be set to FFh.

C3: VRH Setting

Voltage level for VRH.

Parameter byte 1:

Bit    HW Default    TI Default    Description
5:0 0Bh (±4.1V) 03h (±3.7V) VRHS: VRH setting.

C4: VDV Setting

Voltage level for VDV.

Parameter byte 1:

Bit    HW Default    TI Default    Description
5:0 20h (0V) 20h (0V) VDVS: VDV setting.

C5: VCOM Offset Setting

Voltage offset for VCOM, relative to VCOM Setting.

Parameter byte 1:

Bit    HW Default    TI Default    Description
5:0 20h (0V) N/A VCMOFS: VCOM offset setting.

C6: Frame Rate Control 2

Controls the frame rate while in the MCU Interface or VSYNC Interface operating modes.

The refresh rate can be calculated as 10MHz/divisor/(number of lines)/(250+RTNA*16).

Note: The base clock rate of 10MHz varies for each calculator. Some newer datasheets in the ST7789 family indicate a ±5% variance; clock rates have been observed between 9.85 MHz and 10.28 MHz.

The divisor is specified in Frame Rate Control 1.

The number of lines depends on the Porch Setting, and is equal to (BP+320+FP) in MCU Interface mode and a minimum of (BP+320) in VSYNC Interface mode.

If Idle Mode or Partial Mode are active, Frame Rate Control 1's parameters will be used instead if enabled.

Parameter byte 1:

Bit    HW Default    TI Default    Description
4:0 0Fh 0Fh RTNA: Frame rate control for Normal Mode. Affects the duration of each line. See the formula above for how this value is used.

Should be greater than 0, or else the number of pixel clocks per line will be too small for the Internal Reads.

7:5 00h 00h NLA: Polarity inversion method in Normal Mode.
  • 00h: Dot inversion
  • 07h: Line inversion

D0: Power Control 1

Sets power voltages.

Parameter byte 1:

Bit    HW Default    TI Default    Description
7:0 A4h AFh This byte should be A4h according to the datasheet. TI sets it differently.

Parameter byte 2:

Bit    HW Default    TI Default    Description
1:0 01h (6.6V) 01h (6.6V) VDS: VDDS setting.
5:4 02h (-4.8V) 02h (-4.8V) AVCL: AVCL setting.
7:6 02h (6.8V) 02h (6.8V) AVDD: AVDD setting.

D2: Enable VAP/VAN Signal Output

Enables (or disables?) VAP/VAN signal output.

Parameter byte 1:

Bit    HW Default    TI Default    Description
7:0 00h 00h The datasheet is unclear on this. It only specifies 4Ch as a parameter, but 00h as the default. Presumably writing 4Ch enables and writing 00h disables.

DF: Command 2 Enable

Used to enable Command Table 2 when the EXTC pin is low. This command seems to be ignored on the CE, so EXTC is likely high.

If this command was not ignored, a parameter sequence 5Ah, 69h, 02h, 01h would be used to enable Command Table 2.

E0: Positive Voltage Gamma Control

Specifies grayscale voltage parameters when pixels are scanned with positive polarity.

Voltages for gray levels not specified below are evenly spaced linearly between the surrounding specified gray levels.

Additionally, the following levels are linearly interpolated between the surrounding specified gray levels according to the J0P and J1P parameters:

J0P 00h 01h 02h 03h
VP3 50% 56% 50% 60%
VP5 50% 44% 50% 42%
VP7 86% 71% 80% 66%
VP8 71% 57% 63% 49%
VP9 57% 40% 49% 34%
VP10 43% 29% 34% 23%
VP11 29% 17% 20% 14%
VP12 14% 6% 9% 6%
J1P 00h 01h 02h 03h
VP51 86% 86% 86% 89%
VP52 71% 71% 77% 80%
VP53 57% 60% 63% 69%
VP54 43% 46% 46% 51%
VP55 29% 34% 31% 37%
VP56 14% 17% 14% 20%
VP58 50% 56% 47% 47%
VP60 50% 50% 50% 53%

Parameter byte 1:

Bit    HW Default    TI Default    Description
3:0 00h (129) 00h (129) V0P: Voltage for gray level 0 (VP0) is linearly interpolated between VBP and VAP at (129-V0P)/129.
7:4 07h (16) 0Dh (10) V63P: Voltage for gray level 63 (VP63) is linearly interpolated between VBP and VAP at (23-V63P)/129.

Parameter byte 2:

Bit    HW Default    TI Default    Description
5:0 2Ch (84) 00h (128) V1P: Voltage for gray level 1 (VP1) is linearly interpolated between VBP and VAP at (128-V1P)/129.

Parameter byte 3:

Bit    HW Default    TI Default    Description
5:0 2Eh (82) 00h (128) V2P: Voltage for gray level 2 (VP2) is linearly interpolated between VBP and VAP at (128-V2P)/129.

Parameter byte 4:

Bit    HW Default    TI Default    Description
4:0 15h (36) 10h (41) V4P: Voltage for gray level 4 (VP4) is linearly interpolated between VP20 and VP2 at (57-V4P)/60.

Parameter byte 5:

Bit    HW Default    TI Default    Description
4:0 10h (31) 0Fh (32) V6P: Voltage for gray level 6 (VP6) is linearly interpolated between VP20 and VP2 at (47-V6P)/60.

Parameter byte 6:

Bit    HW Default    TI Default    Description
3:0 09h (12) 0Ah (11) V13P: Voltage for gray level 13 (VP13) is linearly interpolated between VP20 and VP2 at (21-V13P)/60.
5:4 00h 01h J0P: Percentage adjustment selection for VP3, VP5, VP7, VP8, VP9, VP10, VP11, and VP12.

Parameter byte 7:

Bit    HW Default    TI Default    Description
6:0 48h (56) 2Dh (83) V20P: Voltage for gray level 20 (VP20) is linearly interpolated between VBP and VAP at (128-V20P)/129.

Parameter byte 8:

Bit    HW Default    TI Default    Description
2:0 03h (17) 04h (16) V27P: Voltage for gray level 27 (VP27) is linearly interpolated between VP43 and VP20 at (20-V27P)/25.
6:4 03h (8) 05h (6) V36P: Voltage for gray level 36 (VP36) is linearly interpolated between VP43 and VP20 at (11-V36P)/25.

Parameter byte 9:

Bit    HW Default    TI Default    Description
6:0 53h (45) 3Fh (65) V43P: Voltage for gray level 43 (VP43) is linearly interpolated between VBP and VAP at (128-V43P)/129.

Parameter byte 10:

Bit    HW Default    TI Default    Description
3:0 0Bh (43) 0Bh (43) V50P: Voltage for gray level 50 (VP50) is linearly interpolated between VP61 and VP43 at (54-V50P)/60.
5:4 00h 03h J1P: Percentage adjustment selection for VP51, VP52, VP53, VP54, VP55, VP56, VP58, and VP60.

Parameter byte 11:

Bit    HW Default    TI Default    Description
4:0 19h (19) 18h (20) V57P: Voltage for gray level 57 (VP57) is linearly interpolated between VP61 and VP43 at (44-V57P)/60.

Parameter byte 12:

Bit    HW Default    TI Default    Description
4:0 18h (10) 17h (11) V59P: Voltage for gray level 59 (VP59) is linearly interpolated between VP61 and VP43 at (34-V59P)/60.

Parameter byte 13:

Bit    HW Default    TI Default    Description
5:0 20h (32) 13h (45) V61P: Voltage for gray level 61 (VP61) is linearly interpolated between VBP and VAP at (64-V61P)/129.

Parameter byte 14:

Bit    HW Default    TI Default    Description
5:0 25h (27) 17h (41) V62P: Voltage for gray level 62 (VP62) is linearly interpolated between VBP and VAP at (64-V62P)/129.

E1: Negative Voltage Gamma Control

Specifies grayscale voltage parameters when pixels are scanned with negative polarity.

Voltages for gray levels not specified below are evenly spaced linearly between the surrounding specified gray levels.

Additionally, the following levels are linearly interpolated between the surrounding specified gray levels according to the J0N and J1N parameters:

J0N 00h 01h 02h 03h
VN3 50% 56% 50% 60%
VN5 50% 44% 50% 42%
VN7 86% 71% 80% 66%
VN8 71% 57% 63% 49%
VN9 57% 40% 49% 34%
VN10 43% 29% 34% 23%
VN11 29% 17% 20% 14%
VN12 14% 6% 9% 6%
J1N 00h 01h 02h 03h
VN51 86% 86% 86% 89%
VN52 71% 71% 77% 80%
VN53 57% 60% 63% 69%
VN54 43% 46% 46% 51%
VN55 29% 34% 31% 37%
VN56 14% 17% 14% 20%
VN58 50% 56% 47% 47%
VN60 50% 50% 50% 53%

Parameter byte 1:

Bit    HW Default    TI Default    Description
3:0 00h (129) 00h (129) V0N: Voltage for gray level 0 (VN0) is linearly interpolated between VBN and VAN at (129-V0N)/129.
7:4 07h (16) 0Dh (10) V63N: Voltage for gray level 63 (VN63) is linearly interpolated between VBN and VAN at (23-V63N)/129.

Parameter byte 2:

Bit    HW Default    TI Default    Description
5:0 2Ch (84) 00h (128) V1N: Voltage for gray level 1 (VN1) is linearly interpolated between VBN and VAN at (128-V1N)/129.

Parameter byte 3:

Bit    HW Default    TI Default    Description
5:0 2Eh (82) 00h (128) V2N: Voltage for gray level 2 (VN2) is linearly interpolated between VBN and VAN at (128-V2N)/129.

Parameter byte 4:

Bit    HW Default    TI Default    Description
4:0 15h (36) 10h (41) V4N: Voltage for gray level 4 (VN4) is linearly interpolated between VN20 and VN2 at (57-V4N)/60.

Parameter byte 5:

Bit    HW Default    TI Default    Description
4:0 10h (31) 0Fh (32) V6N: Voltage for gray level 6 (VN6) is linearly interpolated between VN20 and VN2 at (47-V6N)/60.

Parameter byte 6:

Bit    HW Default    TI Default    Description
3:0 09h (12) 09h (12) V13N: Voltage for gray level 13 (VN13) is linearly interpolated between VN20 and VN2 at (21-V13N)/60.
5:4 00h 00h J0N: Percentage adjustment selection for VN3, VN5, VN7, VN8, VN9, VN10, VN11, and VN12.

Parameter byte 7:

Bit    HW Default    TI Default    Description
6:0 48h (56) 2Bh (85) V20N: Voltage for gray level 20 (VN20) is linearly interpolated between VBN and VAN at (128-V20N)/129.

Parameter byte 8:

Bit    HW Default    TI Default    Description
2:0 03h (17) 03h (17) V27N: Voltage for gray level 27 (VN27) is linearly interpolated between VN43 and VN20 at (20-V27N)/25.
6:4 03h (8) 04h (7) V36N: Voltage for gray level 36 (VN36) is linearly interpolated between VN43 and VN20 at (11-V36N)/25.

Parameter byte 9:

Bit    HW Default    TI Default    Description
6:0 53h (45) 40h (64) V43N: Voltage for gray level 43 (VN43) is linearly interpolated between VBN and VAN at (128-V43N)/129.

Parameter byte 10:

Bit    HW Default    TI Default    Description
3:0 0Bh (43) 0Bh (43) V50N: Voltage for gray level 50 (VN50) is linearly interpolated between VN61 and VN43 at (54-V50N)/60.
5:4 00h 03h J1N: Percentage adjustment selection for VN51, VN52, VN53, VN54, VN55, VN56, VN58, and VN60.

Parameter byte 11:

Bit    HW Default    TI Default    Description
4:0 19h (19) 18h (20) V57N: Voltage for gray level 57 (VN57) is linearly interpolated between VN61 and VN43 at (44-V57N)/60.

Parameter byte 12:

Bit    HW Default    TI Default    Description
4:0 18h (10) 17h (11) V59N: Voltage for gray level 59 (VN59) is linearly interpolated between VN61 and VN43 at (34-V59N)/60.

Parameter byte 13:

Bit    HW Default    TI Default    Description
5:0 20h (32) 13h (45) V61N: Voltage for gray level 61 (VN61) is linearly interpolated between VBN and VAN at (64-V61N)/129.

Parameter byte 14:

Bit    HW Default    TI Default    Description
5:0 25h (27) 17h (41) V62N: Voltage for gray level 62 (VN62) is linearly interpolated between VBN and VAN at (64-V62N)/129.

E2: Digital Gamma LUT for Red

Defines the gamma lookup table for pixels' blue components prior to any BGR swap. The controller enables BGR swap in LCM Control by default, so the datasheet names this as the LUT for red, but according to TI's default settings it applies to blue.

When enabled in Digital Gamma Enable, this LUT is used to translate the 6-bit color component to a new 6-bit value, before displaying to the screen with analog gamma.

For some reason, despite the LUT having 64 entries, the least significant bit of the color component input seems to be forced to 0, so only the even-indexed entries of the LUT are ever accessed. As such, it may be most consistent to write the same value to both even and odd entries, and treat them both as if the desired LSB from the EPF setting in RAM Control was used as the index.

Parameter byte n+1 (n=0 to 63):

Bit    HW Default    TI Default    Description
7:2 n N/A DGM_LUT_Rn: The output mapping when the color component value is equal to n. As mentioned above, when n is odd, the mapping for n-1 is used instead.

E3: Digital Gamma LUT for Blue

Defines the gamma lookup table for pixels' red components prior to any BGR swap. The controller enables BGR swap in LCM Control by default, so the datasheet names this as the LUT for blue, but according to TI's default settings it applies to red.

When enabled in Digital Gamma Enable, this LUT is used to translate the 6-bit color component to a new 6-bit value, before displaying to the screen with analog gamma.

For some reason, despite the LUT having 64 entries, the least significant bit of the color component input seems to be forced to 0, so only the even-indexed entries of the LUT are ever accessed. As such, it may be most consistent to write the same value to both even and odd entries, and treat them both as if the desired LSB from the EPF setting in RAM Control was used as the index.

Parameter byte n+1 (n=0 to 63):

Bit    HW Default    TI Default    Description
7:2 n N/A DGM_LUT_Bn: The output mapping when the color component value is equal to n. As mentioned above, when n is odd, the mapping for n-1 is used instead.

E4: Gate Control

Specifies the physical gates (scanlines) used by the LCD, as well as the scan order.

Parameter byte 1:

Bit    HW Default    TI Default    Description
5:0 27h (320) N/A NL: The number of physical lines in the display is (NL+1)*8. This should always be set to 320 lines on the CE.

Parameter byte 2:

Bit    HW Default    TI Default    Description
5:0 00h (0) N/A SCN: The first physical line in the display is at gate SCN*8. This should always be set to gate 0 on the CE.

Parameter byte 3:

Bit    HW Default    TI Default    Description
0 0 N/A GS: Gate scan direction. 0 means scan in increasing order (left to right), 1 means scan in decreasing order (right to left).

Setting to 1 effectively reverses the display output horizontally. The exact set of gates which are scanned when reversed depends on the TMG bit below.

1 0 N/A SS: Source scan direction. 0 means scan in increasing order (top to bottom), 1 means scan in decreasing order (bottom to top).

Setting to 1 effectively reverses the display output vertically. However, the RGB subpixels are not reversed. Note: This bit is undocumented, always set as 0 in the datasheet.

2 0 N/A SM: Interlaced scan mode. 0 means scan normally, 1 means scan all even lines first, followed by all odd lines.

The pixel data used for the scan is not changed, meaning the first half (normally on the left) is scanned on the even lines and the second half (normally on the right) is scanned on the odd lines.

4 1 N/A TMG: Gate mirror selection. When GS=1, 0 means local mirror across the active gates specified in NL and SCN, and 1 means full mirror across all 320 gates.

In other words, for local mirror, gates [SCN, SCN+NL) are always used, and for full mirror, gates [SCN, SCN+NL) or [320-(SCN+NL), 320-SCN) are used depending on the GS setting.

E9: Equalize Time Control

Specifies equalize and pre-drive times.

Parameter byte 1:

Bit    HW Default    TI Default    Description
4:0 11h 08h SEQ: Source equalize time is SEQ*4 full pixel durations. Minimum value is 1.

Parameter byte 2:

Bit    HW Default    TI Default    Description
4:0 11h 08h SPRET: Source pre-drive time is SPRET*4 full pixel durations. Minimum value is 1.

Parameter byte 3:

Bit    HW Default    TI Default    Description
3:0 08h 08h GEQ: Gate equalize time is GEQ*4 full pixel durations.
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