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| − | [[Category:84PCE:Ports:By_Address|Unknown]] [[Category:84PCE:Ports:By_Name|Unknown]] [[Category:84PCE:Ports:Unknown|Main List]]
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| − | === 0000 Range ===
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| − | {|-
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| − | |<u>Port</u>
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| − | |<u>Default</u>
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| − | |<u>Bits</u>
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| − | |<u>Information</u>
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| − | |-
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| − | |[[:84PCE:Ports:0000|0000]]
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| − | |03
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| − | |D3
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| − | |Upper nibble's functions are unknown
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| − | |-
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| − | |[[:84PCE:Ports:0001|0001]]
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| − | |03
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| − | |13
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| − | |Bit 4's function is unknown
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| − | |-
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| − | |[[:84PCE:Ports:0002|0002]]
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| − | |
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| − | |??
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| − | |Read only, value changes sometimes
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| − | |-
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| − | |[[:84PCE:Ports:0005|0005]]
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| − | |76
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| − | |??
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| − | |Set bit 5 to freeze, bit 6 affects backlight
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| − | |-
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| − | |[[:84PCE:Ports:0006|0006]]
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| − | |03
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| − | |03?
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| − | |Reset bit 1 to disable display refresh
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| − | |-
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| − | |[[:84PCE:Ports:0007|0007]]
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| − | |B7
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| − | |FF
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| − | |Reset bit 1 to cause crash after ? 1 second
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| − | |-
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| − | |[[:84PCE:Ports:0008|0008]]
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| − | |7F
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| − | |??
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| − | |Cannot change value
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| − | |-
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| − | |[[:84PCE:Ports:0009|0009]]
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| − | |
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| − | |??
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| − | |Some values cause a crash
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| − | |-
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| − | |[[:84PCE:Ports:000A|000A]]
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| − | |05
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| − | |??
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| − | |Latches value written, OS reset to 05
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| − | |-
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| − | |[[:84PCE:Ports:000B|000B]]
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| − | |FC
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| − | |??
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| − | |Cannot change value
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| − | |-
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| − | |[[:84PCE:Ports:000C|000C]]
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| − | |00
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| − | |FF
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| − | |Latches value written
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| − | |-
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| − | |[[:84PCE:Ports:000D|000D]]
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| − | |FF
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| − | |FF
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| − | |Bit 0: Freeze if reset<br />Bit 1: Crash if reset<br />Bit 2: No apparent effect if reset<br />Bit 3: Reset to disable VRAM? Upon set, VRAM is garbage.<br />Bits [7:4]Possibly last value written
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| − | |-
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| − | |[[:84PCE:Ports:000E|000E]]
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| − | |0A
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| − | |FF
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| − | |Latches value written
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| − | |-
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| − | |[[:84PCE:Ports:000F|000F]]
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| − | |42
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| − | |?3
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| − | |High nibble may be a status, low 2 bits latch value written
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| − | |-
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| − | |[[:84PCE:Ports:001C|001C]]
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| − | |80
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| − | |??
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| − | |Cannot change value
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| − | |-
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| − | |[[:84PCE:Ports:0028|0028]]
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| − | |
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| − | |FD
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| − | |Bit 1 is always 0, other bits latch value written
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| − | |-
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| − | |[[:84PCE:Ports:0029|0029]]
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| − | |00
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| − | |01
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| − | |Bit 0 latches value written
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| − | |-
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| − | |[[:84PCE:Ports:002A|002A]]
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| − | |70
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| − | |73
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| − | |Latches value written
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| − | |-
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| − | |[[:84PCE:Ports:002B|002B]]
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| − | |FE
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| − | |FF
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| − | |Latches value written
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| − | |-
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| − | |[[:84PCE:Ports:002C|002C]]
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| − | |
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| − | |FF
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| − | |Ports 002C-0031 latch value written
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| − | |-
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| − | |[[:84PCE:Ports:0032|0032]]
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| − | |
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| − | |07
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| − | |Latches value written
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| − | |-
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| − | |[[:84PCE:Ports:0033|0033]]
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| − | |
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| − | |F1
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| − | |Latches value written
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| − | |-
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| − | |[[:84PCE:Ports:0034|0034]]
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| − | |
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| − | |31
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| − | |Latches value written
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| − | |-
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| − | |[[:84PCE:Ports:0035|0035]]
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| − | |
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| − | |3F
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| − | |Latches value written
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| − | |-
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| − | |[[:84PCE:Ports:0036|0036]]
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| − | |
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| − | |FF
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| − | |Ports 0036-003C latch value written
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| − | |-
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| − | |}
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