Difference between revisions of "84PCE:Ports:Control"
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(Fix OS Timer Control and CPU Speed Control being swapped) |
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[[Category:84PCE:Ports:By_Address|Control]] [[Category:84PCE:Ports:By_Name|Control]] | [[Category:84PCE:Ports:By_Address|Control]] [[Category:84PCE:Ports:By_Name|Control]] | ||
| − | |||
== Synopsis == | == Synopsis == | ||
'''Port Number:''' 0000-0fff | '''Port Number:''' 0000-0fff | ||
| Line 6: | Line 5: | ||
'''Function:''' Master Control | '''Function:''' Master Control | ||
| − | This port range is used to configure and control important things; possibly the reason why it does not have a memory-mapped address. | + | This port range is used to configure and control important things; possibly the reason why it does not have a memory-mapped address. It is mirrored every 0x100 bytes. |
If a port is not listed; it indicates that writes have no effect and do not latch, and that reads are 0. Note that this may not be true one hundred percent. | If a port is not listed; it indicates that writes have no effect and do not latch, and that reads are 0. Note that this may not be true one hundred percent. | ||
| + | |||
| + | == Port Address Space == | ||
{|- | {|- | ||
| Line 17: | Line 18: | ||
|[[:84PCE:Ports:0000|0000]] | |[[:84PCE:Ports:0000|0000]] | ||
|03 | |03 | ||
| − | | | + | |OS Timer Control |
|- | |- | ||
|[[:84PCE:Ports:0001|0001]] | |[[:84PCE:Ports:0001|0001]] | ||
|03 | |03 | ||
| − | | | + | |CPU Speed Control |
|- | |- | ||
|[[:84PCE:Ports:0002|0002]] | |[[:84PCE:Ports:0002|0002]] | ||
| Line 28: | Line 29: | ||
|- | |- | ||
|[[:84PCE:Ports:0003|0003]] | |[[:84PCE:Ports:0003|0003]] | ||
| − | |||
| − | |||
|00 | |00 | ||
| + | |Hardware ID | ||
| + | |- | ||
|[[:84PCE:Ports:0005|0005]] | |[[:84PCE:Ports:0005|0005]] | ||
|76 | |76 | ||
| Line 41: | Line 42: | ||
|[[:84PCE:Ports:0007|0007]] | |[[:84PCE:Ports:0007|0007]] | ||
|B7 | |B7 | ||
| − | | | + | |GPIO A DIR |
|- | |- | ||
|[[:84PCE:Ports:0008|0008]] | |[[:84PCE:Ports:0008|0008]] | ||
|7F | |7F | ||
| − | | | + | |GPIO A IN |
|- | |- | ||
|[[:84PCE:Ports:0009|0009]] | |[[:84PCE:Ports:0009|0009]] | ||
|37 | |37 | ||
| − | | | + | |GPIO A OUT |
|- | |- | ||
|[[:84PCE:Ports:000A|000A]] | |[[:84PCE:Ports:000A|000A]] | ||
|FD | |FD | ||
| − | | | + | |GPIO B DIR |
|- | |- | ||
|[[:84PCE:Ports:000B|000B]] | |[[:84PCE:Ports:000B|000B]] | ||
|F8 | |F8 | ||
| − | | | + | |GPIO B IN |
|- | |- | ||
|[[:84PCE:Ports:000C|000C]] | |[[:84PCE:Ports:000C|000C]] | ||
|00 | |00 | ||
| − | | | + | |GPIO B OUT |
|- | |- | ||
|[[:84PCE:Ports:000D|000D]] | |[[:84PCE:Ports:000D|000D]] | ||
|FF | |FF | ||
| − | | | + | |Power control |
|- | |- | ||
|[[:84PCE:Ports:000E|000E]] | |[[:84PCE:Ports:000E|000E]] | ||
| Line 78: | Line 79: | ||
|80 | |80 | ||
|Cannot change value | |Cannot change value | ||
| + | |- | ||
| + | |[[:84PCE:Ports:001D|001D]] | ||
| + | |A7 | ||
| + | |Privileged address | ||
| + | |- | ||
| + | |[[:84PCE:Ports:0020|0020]] | ||
| + | |7C | ||
| + | |Memory protection | ||
|- | |- | ||
|[[:84PCE:Ports:0028|0028]] | |[[:84PCE:Ports:0028|0028]] | ||
| | | | ||
| − | |Bit 1 is always 0 | + | |Bit 1 is always 0 |
|- | |- | ||
|[[:84PCE:Ports:0029|0029]] | |[[:84PCE:Ports:0029|0029]] | ||
Latest revision as of 23:44, 23 April 2021
Synopsis
Port Number: 0000-0fff
Function: Master Control
This port range is used to configure and control important things; possibly the reason why it does not have a memory-mapped address. It is mirrored every 0x100 bytes.
If a port is not listed; it indicates that writes have no effect and do not latch, and that reads are 0. Note that this may not be true one hundred percent.
Port Address Space
| Port | Default | Information |
| 0000 | 03 | OS Timer Control |
| 0001 | 03 | CPU Speed Control |
| 0002 | Read only, value can change | |
| 0003 | 00 | Hardware ID |
| 0005 | 76 | Set bit 5 to freeze, bit 6 affects backlight |
| 0006 | 03 | Display refresh |
| 0007 | B7 | GPIO A DIR |
| 0008 | 7F | GPIO A IN |
| 0009 | 37 | GPIO A OUT |
| 000A | FD | GPIO B DIR |
| 000B | F8 | GPIO B IN |
| 000C | 00 | GPIO B OUT |
| 000D | FF | Power control |
| 000E | 0A | Latches value written |
| 000F | 42 | High nibble may be a status, low 2 bits latch value written |
| 001C | 80 | Cannot change value |
| 001D | A7 | Privileged address |
| 0020 | 7C | Memory protection |
| 0028 | Bit 1 is always 0 | |
| 0029 | 00 | Bit 0 latches value written |
| 002A | 70 | Latches value written |
| 002B | FE | Latches value written |
| 002C | Ports 002C-0031 latch value written | |
| 0032 | Latches value written | |
| 0033 | Latches value written | |
| 0034 | Latches value written | |
| 0035 | Latches value written | |
| 0036 | Ports 0036-0039 latch value written |
