Difference between revisions of "84PCE:Ports:0028"
From WikiTI
(Fix flash unlock sequence.) |
|||
| (3 intermediate revisions by the same user not shown) | |||
| Line 11: | Line 11: | ||
=== Bit [0] === | === Bit [0] === | ||
Latches value written, no apparent effect. | Latches value written, no apparent effect. | ||
| + | |||
| + | Used by OS on Python Edition. | ||
=== Bit [1] === | === Bit [1] === | ||
| Line 16: | Line 18: | ||
=== Bit [2] === | === Bit [2] === | ||
| − | Can be written freely (under the usual | + | Can be written freely (under the usual privileged port constraints). |
=== Bit [3] === | === Bit [3] === | ||
Can be cleared by writing a 0. | Can be cleared by writing a 0. | ||
| − | Gets cleared any time unprivileged code is executed. | + | Gets cleared any time unprivileged code is executed or port 6 bit 2 is reset. |
| − | Fetching a flash unlock sequence ( | + | Fetching a flash unlock sequence (F31800F3ED7EED56ED3928ED3828CB57) that ends in privileged flash while port 6 bit 2 is set is the only way to set it. |
=== Bits [7:4] === | === Bits [7:4] === | ||
Writes do not latch, no apparent effect. | Writes do not latch, no apparent effect. | ||
Latest revision as of 15:29, 8 July 2021
Synopsis
Port Number: 0028
Function: Flash Protection Status
Details
Flash is unlocked if both bits 2 and 3 of this port are set.
Bit [0]
Latches value written, no apparent effect.
Used by OS on Python Edition.
Bit [1]
Always 0, writes do not latch.
Bit [2]
Can be written freely (under the usual privileged port constraints).
Bit [3]
Can be cleared by writing a 0. Gets cleared any time unprivileged code is executed or port 6 bit 2 is reset. Fetching a flash unlock sequence (F31800F3ED7EED56ED3928ED3828CB57) that ends in privileged flash while port 6 bit 2 is set is the only way to set it.
Bits [7:4]
Writes do not latch, no apparent effect.
