Difference between revisions of "83:OS:Memory Mapping"
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<td style="border-left: 1px solid #AAA">ROM0</td> | <td style="border-left: 1px solid #AAA">ROM0</td> | ||
<td>SWAP</td> | <td>SWAP</td> | ||
| − | <td>ROM1/ | + | <td>ROM1/9</td> |
<td>RAM0</td> | <td>RAM0</td> | ||
</tr> | </tr> | ||
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</tr> | </tr> | ||
<tr> | <tr> | ||
| − | <td>1</td><td>1</td><td>0</td><td> | + | <td>1</td><td>1</td><td>0</td><td>1</td> |
<td style="border-left: 1px solid #AAA">ROM0</td> | <td style="border-left: 1px solid #AAA">ROM0</td> | ||
<td>RAM0</td> | <td>RAM0</td> | ||
| Line 99: | Line 99: | ||
</tr> | </tr> | ||
<tr> | <tr> | ||
| − | <td>1</td><td>1</td><td> | + | <td>1</td><td>1</td><td>1</td><td>0</td> |
<td style="border-left: 1px solid #AAA">ROM0</td> | <td style="border-left: 1px solid #AAA">ROM0</td> | ||
<td>RAM0</td> | <td>RAM0</td> | ||
| Line 106: | Line 106: | ||
</tr> | </tr> | ||
<tr> | <tr> | ||
| − | <td>1</td><td>1</td><td> | + | <td>1</td><td>1</td><td>1</td><td>1</td> |
<td style="border-left: 1px solid #AAA">ROM0</td> | <td style="border-left: 1px solid #AAA">ROM0</td> | ||
<td>RAM0</td> | <td>RAM0</td> | ||
Latest revision as of 08:18, 12 June 2009
Memory Mapping
Memory on the TI83 has been split up in 16Kb pages. The 256Kb of ROM has been split up in 16 such pages. The 32Kb of RAM have been split up in 2 pages.
The following table describes how these pages are mapped to the 16 bit address space of the z80 depending on the value of various I/O ports.
| Port 04 bit 0 | Port 02 bit 6 | Port 02 bit 7 | Port 02 bit 3 | 0x0000 | 0x4000 | 0x8000 | 0xC000 |
|---|---|---|---|---|---|---|---|
| 0 | * | 0 | 0 | ROM0 | SWAP | ROM0/8 | RAM0 |
| 0 | * | 0 | 1 | ROM0 | SWAP | ROM1/9 | RAM0 |
| 0 | * | 1 | 0 | ROM0 | SWAP | RAM0 | RAM0 |
| 0 | * | 1 | 1 | ROM0 | SWAP | RAM1 | RAM0 |
| 1 | 0 | 0 | 0 | ROM0 | ROM0/8 | SWAP | ROM0/8 |
| 1 | 0 | 0 | 1 | ROM0 | ROM0/8 | SWAP | ROM1/9 |
| 1 | 0 | 1 | 0 | ROM0 | ROM0/8 | SWAP | RAM0 |
| 1 | 0 | 1 | 1 | ROM0 | ROM0/8 | SWAP | RAM1 |
| 1 | 1 | 0 | 0 | ROM0 | RAM0 | RAM1 | ROM0/8 |
| 1 | 1 | 0 | 1 | ROM0 | RAM0 | RAM1 | ROM1/9 |
| 1 | 1 | 1 | 0 | ROM0 | RAM0 | RAM1 | RAM0 |
| 1 | 1 | 1 | 1 | ROM0 | RAM0 | RAM1 | RAM1 |
- RAMx = RAM Page x
- ROMx = ROM Page x
- ROMx/y = ROM Page x or y depending on bit 4 of port 00.
- SWAP = Page swappable through port 02 bits 0, 1, 2 and 6 and port 00 bit 4.
The line in italics is the default mode.
