Difference between revisions of "83Plus:Ports:21"

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[[Category:83Plus:Ports:By_Address:Protected|21 - Flash Type / RAM Protection]] [[Category:83Plus:Ports:By_Address|21 - Flash Type / RAM Protection]] [[Category:83Plus:Ports:By_Name|Flash Type / RAM Protection]]
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[[Category:83Plus:Ports:By_Address:Protected|21 - Flash Size / RAM Size]] [[Category:83Plus:Ports:By_Address|21 - Flash Size/ RAM Size]] [[Category:83Plus:Ports:By_Name|Flash Size/ RAM Size]]
 
{{SE-Only Port|01}}
 
{{SE-Only Port|01}}
 
{{Protected Port}}
 
{{Protected Port}}
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'''Port Number:''' 21h
 
'''Port Number:''' 21h
  
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'''Function:''' Flash Type / RAM Protection
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'''Function:''' Flash Size / RAM Size
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The lower nibble of this port is related to flash. Specifically, the boot code sets bit 0 to 0 to indicate that a 1 MB flash chip is installed, and 1 to indicate that a 2 MB flash chip is installed. The high nibble is part of the RAM execution protection.
+
  
 
=== Read Values ===
 
=== Read Values ===
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* Bit 0: 1 on either the 83+ SE or the 84+ SE, 0 on the 84+ basic.
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* Bits 0-1: Set flash chip size (see below)
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* Bit 1: Always set to zero
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* Bits 4-5: Set RAM chip size (see below)
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* Bits 4-5: current RAM protection mode (see below)
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=== Write Values ===
 
=== Write Values ===
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This port does not exist on the standard 83+.  See [[83Plus:Ports:02|port 2]].
 
This port does not exist on the standard 83+.  See [[83Plus:Ports:02|port 2]].
  
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The value of this port is initialized by the boot code to either 01 (TI-83+ SE, TI-84+ SE) or 00 (TI-84+ basic.)  Bit 0 can thus be used to determine the hardware type (in fact, the OS checks both bits 0 and 1, by ANDing the value with 3; it may be a good idea for user programs to do the same.)
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The value of this port is initialized by the boot code. On the TI-83+SE, TI-84+, and TI-84+SE, bit 0 can be used to determine the hardware type alone. On the TI-84+CSE, use bits 1 and 0. If want to run on the TI-83+SE through TI+84+CSE for some reason, check both bits. The OS likes to check both bits by doing AND 3.
 +
 
 +
=== Flash Chip Size ===
 +
The lower nibble controls the flash chip type. See also [[83Plus:Memory_Mapping]]. Flash pages have three different properties determined by this port: readable/censored, privileged/unprivileged, and mutable/immutable. The only censored page is the certificate page. Privileged pages can unlock flash via [[83Plus:Ports:14|port 14]]. Immutable pages cannot be written to even when flash is unlocked.
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{|-
 +
|<u>Value</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Chip Size</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Boot Page(s)</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Certificate</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Privileged</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Immutable</u>&nbsp;&nbsp;&nbsp;
 +
|-
 +
|0
 +
|1024 K
 +
|3F
 +
|3E
 +
|2C-2F & 3C-3F
 +
|2C-2F & 3F
 +
|-
 +
|1
 +
|2048 K
 +
|7F
 +
|7E
 +
|6C-6F & 7C-7F
 +
|6C-6F & 7F
 +
|-
 +
|2
 +
|4096 K
 +
|FF
 +
|FE
 +
|EC-EF & FC-FF
 +
|EC-EF & FF
 +
|-
 +
|3
 +
|8192 K
 +
|1FF
 +
|1FE
 +
|1EC-1EF & 1FC-1FF&nbsp;&nbsp;&nbsp;
 +
|1EC-1EF & 1FF
 +
|}
  
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=== RAM protection modes ===
 
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Which RAM addresses are executable is determined by ports 25 and 26. The high nibble of port 21 controls how frequently the RAM protection loops. It will loop every 2^(value+1) pages. So, 0 loops every 2 pages, and 3 loops every 16 pages (in other words, not at all).
 
  
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With the default values of 10h and 20h in ports 25 and 26:
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=== RAM Chip Size ===
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* '''Mode 0''' (the default): Execution is allowed on pages 81h, 83h, 85h, 87h, 89h, 8Bh, 8Dh, and 8Fh.
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The TI-83+SE had an external RAM chip. This port therefore informs the ASIC what size RAM chip is installed.
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* '''Mode 1*''': Execution is allowed on pages 81h, 85h, 89h, and 8Dh.
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* '''Mode 2*''': Execution is allowed on pages 81h and 89h.
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* '''Mode 3*''': Execution is allowed on pages 81h only.
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''* In modes 1 to 3, execution is also allowed on the first 1024 bytes of each page immediately following a normally allowed page because TI screwed up on [[83Plus:Ports:26|port 26h]].''
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{|-
 +
|<u>Value</u>&nbsp;&nbsp;&nbsp;
 +
|<u>Chip Size</u>&nbsp;&nbsp;&nbsp;
 +
|-
 +
|0
 +
|32K
 +
|-
 +
|1
 +
|64 K
 +
|-
 +
|2
 +
|128 K
 +
|-
 +
|3
 +
|256 K
 +
|-
 +
|}
  
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(If you ever attempt to execute code from a "disallowed" page, the calculator resets.)
+
The actual execution permissions of RAM pages are masked by this port. Because TI sets it 0 (instead of 2), the ASIC thinks there's 32 K of RAM, and allows execution on all odd-numbered pages, instead of just 81h like TI intended. (If you set this to 1, 2, or 3, execution is also allowed on the first 1024 bytes of each page immediately following an allowed page because TI screwed up on [[83Plus:Ports:26#Comments|port 26h]].) If you ever attempt to execute code from a non-executable page, the calculator resets.
  
 
== Example ==
 
== Example ==

Latest revision as of 17:32, 20 February 2013

This port only exists as a distinct port on the TI-83 Plus Silver Edition, the TI-84 Plus, and the TI-84 Plus Silver Edition. On the standard TI-83 Plus, it acts as a shadow of port 01.
This port is protected, which means user programs cannot ordinarily write to it directly.

Synopsis

Port Number: 21h

Function: Flash Size / RAM Size

Read Values

  • Bits 0-1: Set flash chip size (see below)
  • Bits 4-5: Set RAM chip size (see below)

Write Values

  • Bits 0, 1, 4, 5: set new values for these bits.
  • Bits 2, 3, 6, 7: ignored

Comments

This port does not exist on the standard 83+. See port 2.

The value of this port is initialized by the boot code. On the TI-83+SE, TI-84+, and TI-84+SE, bit 0 can be used to determine the hardware type alone. On the TI-84+CSE, use bits 1 and 0. If want to run on the TI-83+SE through TI+84+CSE for some reason, check both bits. The OS likes to check both bits by doing AND 3.

Flash Chip Size

The lower nibble controls the flash chip type. See also 83Plus:Memory_Mapping. Flash pages have three different properties determined by this port: readable/censored, privileged/unprivileged, and mutable/immutable. The only censored page is the certificate page. Privileged pages can unlock flash via port 14. Immutable pages cannot be written to even when flash is unlocked.

Value    Chip Size    Boot Page(s)    Certificate    Privileged    Immutable   
0 1024 K 3F 3E 2C-2F & 3C-3F 2C-2F & 3F
1 2048 K 7F 7E 6C-6F & 7C-7F 6C-6F & 7F
2 4096 K FF FE EC-EF & FC-FF EC-EF & FF
3 8192 K 1FF 1FE 1EC-1EF & 1FC-1FF    1EC-1EF & 1FF


RAM Chip Size

The TI-83+SE had an external RAM chip. This port therefore informs the ASIC what size RAM chip is installed.

Value    Chip Size   
0 32K
1 64 K
2 128 K
3 256 K

The actual execution permissions of RAM pages are masked by this port. Because TI sets it 0 (instead of 2), the ASIC thinks there's 32 K of RAM, and allows execution on all odd-numbered pages, instead of just 81h like TI intended. (If you set this to 1, 2, or 3, execution is also allowed on the first 1024 bytes of each page immediately following an allowed page because TI screwed up on port 26h.) If you ever attempt to execute code from a non-executable page, the calculator resets.

Example

	in a,(2)
	ld b,a
	and 80h
	jr z,TI83p_BE
	in a,(21h)
	and 3
	jr z,TI84p_BE
	bit 5,b
	jr z,TI83p_SE
	; calculator is an 84+ SE

TI84p_BE:
	; calculator is an 84+ BE

TI83p_SE:
	; calculator is an 83+ SE

TI83p_BE:
	; calculator is an 83+ BE
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