Difference between revisions of "84PCE:Ports:7000"
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Calc84maniac (Talk | contribs) (Updated with full documentation) |
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| − | [[Category:84PCE:Ports:By_Address|7000 - | + | [[Category:84PCE:Ports:By_Address|7000 - General-Purpose Timers]] [[Category:84PCE:Ports:By_Name|General-Purpose Timers]] |
== Synopsis == | == Synopsis == | ||
| − | '''Port Number:''' 7000- | + | '''Port Number:''' 7000-703F |
'''Memory-mapped address:''' F20000 | '''Memory-mapped address:''' F20000 | ||
| − | '''Function:''' | + | '''Function:''' General-Purpose Timers |
| − | This range appears to | + | This range provides three general-purpose 32-bit timers (appears to be model FTTMR010). They can count up or down, and run at either 32768Hz or the CPU clock speed. The counters can generate interrupts either when looping or when matching one of two customizable values. The OS uses the third timer when USB is connected. |
| + | |||
| + | == Registers == | ||
| + | All registers are little-endian and cross multiple 8-bit ports. | ||
| + | * Timers 1, 2, 3: | ||
| + | ** 7000, 7010, 7020 (R/W): | ||
| + | *** 32-bit counter register. Can be written directly, but it should be disabled first since the entire value cannot be written atomically. | ||
| + | ** 7004, 7014, 7024 (R/W): | ||
| + | *** 32-bit reload register. The counter is reloaded with this value once it reaches 0. | ||
| + | ** 7008, 7018, 7028 (R/W): | ||
| + | *** 32-bit match register 1. An interrupt will be generated when the counter matches this value. | ||
| + | ** 700C, 701C, 702C (R/W): | ||
| + | *** 32-bit match register 2. An interrupt will be generated when the counter matches this value. | ||
| + | ** 7030 (R/W): 12-bit control register. | ||
| + | *** Bits 0,3,6: Timer enable. Set to enable the corresponding timer. | ||
| + | *** Bits 1,4,7: Clock source. Set to 1 to use the 32768Hz clock, or 0 to use the CPU clock. | ||
| + | *** Bits 2,5,8: Overflow interrupt enable. Set to generate an interrupt when the counter reaches 0. | ||
| + | *** Bits 9,10,11: Count direction. Set to 1 to count up, or 0 to count down. | ||
| + | ** 7034 (R/W): 12-bit interrupt status register. Reads the cause of the interrupt. Write 1 bits to reset. | ||
| + | *** Bits 0,3,6: Match 1. Set after the counter reaches match register 1. | ||
| + | *** Bits 1,4,7: Match 2. Set after the counter reaches match register 2. | ||
| + | *** Bits 2,5,8: Overflow. Set after the counter reaches 0 and gets reloaded, but only if enabled in the control register. | ||
| + | ** 7038 (R/W): 12-bit interrupt mask? Seems to have no effect on interrupt generation, however. | ||
| + | ** 703C (R): | ||
| + | *** 32-bit revision register. Reads a constant 0x00010801, which corresponds to revision 1.8.1. | ||
Revision as of 22:38, 3 April 2015
Synopsis
Port Number: 7000-703F
Memory-mapped address: F20000
Function: General-Purpose Timers
This range provides three general-purpose 32-bit timers (appears to be model FTTMR010). They can count up or down, and run at either 32768Hz or the CPU clock speed. The counters can generate interrupts either when looping or when matching one of two customizable values. The OS uses the third timer when USB is connected.
Registers
All registers are little-endian and cross multiple 8-bit ports.
- Timers 1, 2, 3:
- 7000, 7010, 7020 (R/W):
- 32-bit counter register. Can be written directly, but it should be disabled first since the entire value cannot be written atomically.
- 7004, 7014, 7024 (R/W):
- 32-bit reload register. The counter is reloaded with this value once it reaches 0.
- 7008, 7018, 7028 (R/W):
- 32-bit match register 1. An interrupt will be generated when the counter matches this value.
- 700C, 701C, 702C (R/W):
- 32-bit match register 2. An interrupt will be generated when the counter matches this value.
- 7030 (R/W): 12-bit control register.
- Bits 0,3,6: Timer enable. Set to enable the corresponding timer.
- Bits 1,4,7: Clock source. Set to 1 to use the 32768Hz clock, or 0 to use the CPU clock.
- Bits 2,5,8: Overflow interrupt enable. Set to generate an interrupt when the counter reaches 0.
- Bits 9,10,11: Count direction. Set to 1 to count up, or 0 to count down.
- 7034 (R/W): 12-bit interrupt status register. Reads the cause of the interrupt. Write 1 bits to reset.
- Bits 0,3,6: Match 1. Set after the counter reaches match register 1.
- Bits 1,4,7: Match 2. Set after the counter reaches match register 2.
- Bits 2,5,8: Overflow. Set after the counter reaches 0 and gets reloaded, but only if enabled in the control register.
- 7038 (R/W): 12-bit interrupt mask? Seems to have no effect on interrupt generation, however.
- 703C (R):
- 32-bit revision register. Reads a constant 0x00010801, which corresponds to revision 1.8.1.
- 7000, 7010, 7020 (R/W):
