Difference between revisions of "84PCE:Ports:5000"
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| Line 9: | Line 9: | ||
|0 | |0 | ||
|ON Button | |ON Button | ||
| + | |- | ||
| + | |1 | ||
| + | |Timer 1 | ||
| + | |- | ||
| + | |2 | ||
| + | |Timer 2 | ||
| + | |- | ||
| + | |3 | ||
| + | |Timer 3 | ||
|- | |- | ||
|4 | |4 | ||
| Line 18: | Line 27: | ||
|11 | |11 | ||
|LCD Controller | |LCD Controller | ||
| + | |- | ||
| + | |12 | ||
| + | |RTC, perhaps? Seems to trigger on the minute by default. | ||
|- | |- | ||
|15 | |15 | ||
Revision as of 22:46, 3 April 2015
This port range has an interesting semi-pattern of read-only and latching ports. Some of these ports have a critical function for interrupt-handling. A partial list is below, but ports with some kind of function continue until at least 5055.
It seems to be arranged in 22-bit bitfields (each occupying a little-endian 32-bit word), with each bit corresponding to a different interrupt source. Known sources so far:
| Bit | Interrupt Source |
| 0 | ON Button |
| 1 | Timer 1 |
| 2 | Timer 2 |
| 3 | Timer 3 |
| 4 | Unknown, but disabling causes freeze (might be OS timer?) |
| 10 | Keyboard |
| 11 | LCD Controller |
| 12 | RTC, perhaps? Seems to trigger on the minute by default. |
| 15 | Unknown, but signal seems to be constantly on |
This range is (probably?) memory-mapped to F00000.
| Port | Default | Bits | Information |
| 5000 | Read-Only | 003FFFFF | Raw interrupt status (can be either raw signal or latched on signal change from low-to-high). |
| 5004 | 00003011 | 003FFFFF | Interrupt enable mask. |
| 5008 | Write-Only | 003FFFFF | Interrupt acknowledge (used by ISR), seems to only affect latched status bits. |
| 500C | 00000019 | 003FFFFF | Determines whether bits of 5000 will latch. 0 means raw signal, 1 means latched. |
| 5010 | 00000000 | 003FFFFF | Inverts the raw signal of the interrupts corresponding to each 1 bit. Can be used to latch on a high-to-low change. |
| 5014 | Read-only | 003FFFFF | Masked interrupt status (used by ISR). Should be equal to (5000 & 5004). |
| 5018 | Read-only | ???????? | Ports 5018-501F may always read zero |
| 5020 | Ports 5020-503F seem to be identical in function to 5000-501F (but not mirrors). These registers do not seem to actually trigger interrupts. Assuming this chip was meant for use with ARM, this would likely have been intended to drive the FIQ signal, but the eZ80 has no such alternative interrupts. |
