Difference between revisions of "84PCE:Ports:4000"

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(Add datasheet for LCD controller)
Line 10: Line 10:
  
 
Datasheet: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0293c/DDI0293.pdf
 
Datasheet: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0293c/DDI0293.pdf
 +
 +
== PL111 Register Summary ==
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDTiming0
 +
| 0x000
 +
| R/W
 +
| 0x00000000
 +
| Horizontal Axis Panel Control Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDTiming1
 +
| 0x004
 +
| R/W
 +
| 0x00000000
 +
| Vertical Axis Panel Control Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDTiming2
 +
| 0x008
 +
| R/W
 +
| 0x00000000
 +
| Clock and Signal Polarity Control Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDTiming3
 +
| 0x00C
 +
| R/W
 +
| 0x00000
 +
| Line End Control Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDUPBASE
 +
| 0x010
 +
| R/W
 +
| 0x00000000
 +
| Upper and Lower Panel Frame Base Address Registers
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDLPBASE
 +
| 0x014
 +
| R/W
 +
| 0x00000000
 +
| Upper and Lower Panel Frame Base Address Registers
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDControl
 +
| 0x018
 +
| R/W
 +
| 0x0000
 +
| LCD Control Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDIMSC
 +
| 0x01C
 +
| R/W
 +
| 0x0
 +
| Interrupt Mask Set/Clear Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDRIS
 +
| 0x020
 +
| RO
 +
| 0x0
 +
| Raw Interrupt Status Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDMIS
 +
| 0x024
 +
| RO
 +
| 0x0
 +
| Masked Interrupt Status Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDICR
 +
| 0x028
 +
| WO
 +
| 0x0
 +
| LCD Interrupt Clear Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDUPCURR
 +
| 0x02C
 +
| RO
 +
| 0x00000000
 +
| LCD Upper and Lower Panel Current Address Value Registers
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDLPCURR
 +
| 0x030
 +
| RO
 +
| 0x00000000
 +
| LCD Upper and Lower Panel Current Address Value Registers
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| -
 +
| 0x034-0x1FC
 +
| -
 +
| -
 +
| Reserved
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| LCDPalette
 +
| 0x200-0x3FC
 +
| R/W
 +
| 0x00000000
 +
| 256x16-bit Color Palette Registers
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| -
 +
| 0x400-0x7FC
 +
| -
 +
| -
 +
| Reserved
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| CursorImage
 +
| 0x800-0xBFC
 +
| R/W
 +
| 0x00000000
 +
| Cursor Image RAM Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| ClcdCrsrCtrl
 +
| 0xC00
 +
| R/W
 +
| 0x00
 +
| Cursor Control Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| ClcdCrsrConfig
 +
| 0xC04
 +
| R/W
 +
| 0x0
 +
| Cursor Configuration Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| ClcdCrsrPalette0
 +
| 0xC08
 +
| R/W
 +
| 0x000000
 +
| Cursor Palette Registers
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| ClcdCrsrPalette1
 +
| 0xC0C
 +
| R/W
 +
| 0x000000
 +
| Cursor Palette Registers
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| ClcdCrsrXY
 +
| 0xC10
 +
| R/W
 +
| 0x00000000
 +
| Cursor XY Position Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| ClcdCrsrClip
 +
| 0xC14
 +
| R/W
 +
| 0x0000
 +
| Cursor Clip Position Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| -
 +
| 0xC18-0xC1C
 +
| -
 +
| -
 +
| Reserved
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| ClcdCrsrIMSC
 +
| 0xC20
 +
| R/W
 +
| 0x0
 +
| Cursor Interrupt Mask Set/Clear Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| ClcdCrsrICR
 +
| 0xC24
 +
| WO
 +
| 0x0
 +
| Cursor Interrupt Clear Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| ClcdCrsrRIS
 +
| 0xC28
 +
| RO
 +
| 0x0
 +
| Cursor Raw Interrupt Status Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| ClcdCrsrMIS
 +
| 0xC2C
 +
| RO
 +
| 0x0
 +
| Cursor Masked Interrupt Status Register
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| -
 +
| 0xC30-0xDFC
 +
| -
 +
| -
 +
| Reserved
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| -
 +
| 0xF00-0xF08
 +
| -
 +
| -
 +
| Programmers Model for Test
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| -
 +
| 0xF0C-0xFDC
 +
| -
 +
| -
 +
| Reserved
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| CLCDPeriphID0
 +
| 0xFE0
 +
| RO
 +
| 0x11
 +
| Peripheral Identification Register 0
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| CLCDPeriphID1
 +
| 0xFE4
 +
| RO
 +
| 0x11
 +
| Peripheral Identification Register 1
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| CLCDPeriphID2
 +
| 0xFE8
 +
| RO
 +
| 0x-4a
 +
| Peripheral Identification Register 2
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| CLCDPeriphID3
 +
| 0xFEC
 +
| RO
 +
| 0x00
 +
| Peripheral Identification Register 3
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| CLCDPCellID0
 +
| 0xFF0
 +
| RO
 +
| 0x0D
 +
| PrimeCell Identification Register 0
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| CLCDPCellID1
 +
| 0xFF4
 +
| RO
 +
| 0xF0
 +
| PrimeCell Identification Register 1
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| CLCDPCellID2
 +
| 0xFF8
 +
| RO
 +
| 0x05
 +
| PrimeCell Identification Register 2
 +
|}
 +
<br>
 +
 +
{|border="1" cellspacing="0" cellpadding="5"
 +
|-
 +
! Name
 +
! Base Offset
 +
! Type
 +
! Reset Value
 +
! Dscription
 +
|-
 +
| CLCDPCellID3
 +
| 0xFFC
 +
| RO
 +
| 0xB1
 +
| PrimeCell Identification Register 3
 +
|}
 +
<br>

Revision as of 19:45, 8 April 2015

Synopsis

Port Number: 4000

Memory-mapped address: E30000

Function: LCD Controller

The ports in this range are for accessing the LCD controller. With these ports, you can configure the LCD DMA address, change the color mode, access the palette, alter the LCD cursor, and possibly other useful things.

Datasheet: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0293c/DDI0293.pdf

PL111 Register Summary

Name Base Offset Type Reset Value Dscription
LCDTiming0 0x000 R/W 0x00000000 Horizontal Axis Panel Control Register


Name Base Offset Type Reset Value Dscription
LCDTiming1 0x004 R/W 0x00000000 Vertical Axis Panel Control Register


Name Base Offset Type Reset Value Dscription
LCDTiming2 0x008 R/W 0x00000000 Clock and Signal Polarity Control Register


Name Base Offset Type Reset Value Dscription
LCDTiming3 0x00C R/W 0x00000 Line End Control Register


Name Base Offset Type Reset Value Dscription
LCDUPBASE 0x010 R/W 0x00000000 Upper and Lower Panel Frame Base Address Registers


Name Base Offset Type Reset Value Dscription
LCDLPBASE 0x014 R/W 0x00000000 Upper and Lower Panel Frame Base Address Registers


Name Base Offset Type Reset Value Dscription
LCDControl 0x018 R/W 0x0000 LCD Control Register


Name Base Offset Type Reset Value Dscription
LCDIMSC 0x01C R/W 0x0 Interrupt Mask Set/Clear Register


Name Base Offset Type Reset Value Dscription
LCDRIS 0x020 RO 0x0 Raw Interrupt Status Register


Name Base Offset Type Reset Value Dscription
LCDMIS 0x024 RO 0x0 Masked Interrupt Status Register


Name Base Offset Type Reset Value Dscription
LCDICR 0x028 WO 0x0 LCD Interrupt Clear Register


Name Base Offset Type Reset Value Dscription
LCDUPCURR 0x02C RO 0x00000000 LCD Upper and Lower Panel Current Address Value Registers


Name Base Offset Type Reset Value Dscription
LCDLPCURR 0x030 RO 0x00000000 LCD Upper and Lower Panel Current Address Value Registers


Name Base Offset Type Reset Value Dscription
- 0x034-0x1FC - - Reserved


Name Base Offset Type Reset Value Dscription
LCDPalette 0x200-0x3FC R/W 0x00000000 256x16-bit Color Palette Registers


Name Base Offset Type Reset Value Dscription
- 0x400-0x7FC - - Reserved


Name Base Offset Type Reset Value Dscription
CursorImage 0x800-0xBFC R/W 0x00000000 Cursor Image RAM Register


Name Base Offset Type Reset Value Dscription
ClcdCrsrCtrl 0xC00 R/W 0x00 Cursor Control Register


Name Base Offset Type Reset Value Dscription
ClcdCrsrConfig 0xC04 R/W 0x0 Cursor Configuration Register


Name Base Offset Type Reset Value Dscription
ClcdCrsrPalette0 0xC08 R/W 0x000000 Cursor Palette Registers


Name Base Offset Type Reset Value Dscription
ClcdCrsrPalette1 0xC0C R/W 0x000000 Cursor Palette Registers


Name Base Offset Type Reset Value Dscription
ClcdCrsrXY 0xC10 R/W 0x00000000 Cursor XY Position Register


Name Base Offset Type Reset Value Dscription
ClcdCrsrClip 0xC14 R/W 0x0000 Cursor Clip Position Register


Name Base Offset Type Reset Value Dscription
- 0xC18-0xC1C - - Reserved


Name Base Offset Type Reset Value Dscription
ClcdCrsrIMSC 0xC20 R/W 0x0 Cursor Interrupt Mask Set/Clear Register


Name Base Offset Type Reset Value Dscription
ClcdCrsrICR 0xC24 WO 0x0 Cursor Interrupt Clear Register


Name Base Offset Type Reset Value Dscription
ClcdCrsrRIS 0xC28 RO 0x0 Cursor Raw Interrupt Status Register


Name Base Offset Type Reset Value Dscription
ClcdCrsrMIS 0xC2C RO 0x0 Cursor Masked Interrupt Status Register


Name Base Offset Type Reset Value Dscription
- 0xC30-0xDFC - - Reserved


Name Base Offset Type Reset Value Dscription
- 0xF00-0xF08 - - Programmers Model for Test


Name Base Offset Type Reset Value Dscription
- 0xF0C-0xFDC - - Reserved


Name Base Offset Type Reset Value Dscription
CLCDPeriphID0 0xFE0 RO 0x11 Peripheral Identification Register 0


Name Base Offset Type Reset Value Dscription
CLCDPeriphID1 0xFE4 RO 0x11 Peripheral Identification Register 1


Name Base Offset Type Reset Value Dscription
CLCDPeriphID2 0xFE8 RO 0x-4a Peripheral Identification Register 2


Name Base Offset Type Reset Value Dscription
CLCDPeriphID3 0xFEC RO 0x00 Peripheral Identification Register 3


Name Base Offset Type Reset Value Dscription
CLCDPCellID0 0xFF0 RO 0x0D PrimeCell Identification Register 0


Name Base Offset Type Reset Value Dscription
CLCDPCellID1 0xFF4 RO 0xF0 PrimeCell Identification Register 1


Name Base Offset Type Reset Value Dscription
CLCDPCellID2 0xFF8 RO 0x05 PrimeCell Identification Register 2


Name Base Offset Type Reset Value Dscription
CLCDPCellID3 0xFFC RO 0xB1 PrimeCell Identification Register 3


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