Difference between revisions of "User:CoBB"

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(→‎Reference)
(→‎Z80 instruction set)
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| dec J || <tt>11i11101 0010b101</tt> || 8 || + || + || + || + || + || V || 1 || - || J -= 1
 
| dec J || <tt>11i11101 0010b101</tt> || 8 || + || + || + || + || + || V || 1 || - || J -= 1
 
|-
 
|-
−
| dec (hl) || <tt>00110101</tt> || 7 || + || + || + || + || + || V || 1 || - || (hl) -= 1
+
| dec (hl) || <tt>00110101</tt> || 11 || + || + || + || + || + || V || 1 || - || (hl) -= 1
 
|-
 
|-
 
| dec (I+D) || <tt>11i11101 00110101 dddddddd</tt> || 19 || + || + || + || + || + || V || 1 || - || (I+D) -= 1
 
| dec (I+D) || <tt>11i11101 00110101 dddddddd</tt> || 19 || + || + || + || + || + || V || 1 || - || (I+D) -= 1
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|-
 
|-
 
| ei || <tt>11111011</tt> || 4 || - || - || - || - || - || - || - || - || iff1 := 1, iff2 := 1 after the next instruction
 
| ei || <tt>11111011</tt> || 4 || - || - || - || - || - || - || - || - || iff1 := 1, iff2 := 1 after the next instruction
 +
|-
 +
| ex (sp),hl || <tt>11100011</tt> || 19 || - || - || - || - || - || - || - || - || (sp) <=> hl
 +
|-
 +
| ex (sp),I || <tt>11i11101 11100011</tt> || 23 || - || - || - || - || - || - || - || - || (sp) <=> I
 +
|-
 +
| ex af,af' || <tt>00001000</tt> || 4 || X || X || X || X || X || X || X || X || af <=> af'
 +
|-
 +
| ex de,hl || <tt>11101011</tt> || 4 || - || - || - || - || - || - || - || - || de <=> hl
 +
|-
 +
| exx || <tt>11011001</tt> || 4 || - || - || - || - || - || - || - || - || bc, de, hl <=> bc', de', hl'
 +
|-
 +
| halt || <tt>01110110</tt> || 4 || - || - || - || - || - || - || - || - || wait for interrupt
 +
|-
 +
| im 0 || <tt>11101101 01000110</tt> || 8 || - || - || - || - || - || - || - || - || mode 0: execute instruction on bus
 +
|-
 +
| im 1 || <tt>11101101 01010110</tt> || 8 || - || - || - || - || - || - || - || - || mode 1: execute rst $38
 +
|-
 +
| im 2 || <tt>11101101 01011110</tt> || 8 || - || - || - || - || - || - || - || - || mode 2: call (i * 256 + byte on bus)
 +
|-
 +
| in a,(N) || <tt>11011011 nnnnnnnn</tt> || 11 || - || - || - || - || - || - || - || - || a := ((N))
 +
|-
 +
| in R,(c) || <tt>11101101 01rrr000</tt> || 12 || + || + || + || 0 || + || P || 0 || - || R := ((c))
 +
|-
 +
| in f,(c) || <tt>11101101 01110000</tt> || 12 || + || + || + || 0 || + || P || 0 || - || ((c)) => flags
 +
|-
 +
| inc R || <tt>00rrr100</tt> || 4 || + || + || + || + || + || V || 0 || - || R += 1
 +
|-
 +
| inc J || <tt>11i11101 0010b100</tt> || 8 || + || + || + || + || + || V || 0 || - || J += 1
 +
|-
 +
| inc (hl) || <tt>00110100</tt> || 11 || + || + || + || + || + || V || 0 || - || (hl) += 1
 +
|-
 +
| inc (I+D) || <tt>11i11101 00110100 dddddddd</tt> || 23 || + || + || + || + || + || V || 0 || - || (I+D) += 1
 +
|-
 +
| inc Q || <tt>00qq0011</tt> || 6 || - || - || - || - || - || - || - || - || Q += 1
 +
|-
 +
| inc I || <tt>11i11101 00100011</tt> || 10 || - || - || - || - || - || - || - || - || I += 1
 
|-
 
|-
 
| ld R1,R2 || <tt>01rrrsss</tt> || 4 || - || - || - || - || - || - || - || - || R1 := R2
 
| ld R1,R2 || <tt>01rrrsss</tt> || 4 || - || - || - || - || - || - || - || - || R1 := R2
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=== Miscellaneous ===
 
=== Miscellaneous ===
 
* () = indirection
 
* () = indirection
 +
* (()) = I/O port
 
* [] = operator precedence (to avoid confusion with indirection)
 
* [] = operator precedence (to avoid confusion with indirection)
 
* E.B = the Bth bit of the value of expression E
 
* E.B = the Bth bit of the value of expression E

Revision as of 23:15, 1 March 2006

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Z80 instruction set

Reference

Instruction Opcode Time S Z X H Y P N C Effect
adc a,R 10001rrr 4 + + + + + V 0 + a += R + cf
adc a,J 11i11101 1000110b 8 + + + + + V 0 + a += J + cf
adc a,N 11001110 nnnnnnnn 7 + + + + + V 0 + a += N + cf
adc a,(hl) 10001110 7 + + + + + V 0 + a += (hl) + cf
adc a,(I+D) 11i11101 10001110 dddddddd 19 + + + + + V 0 + a += (I+D) + cf
adc hl,Q 11101101 01qq1010 15 + + + + + V 0 + hl += Q + cf
add a,R 10000rrr 4 + + + + + V 0 + a += R
add a,J 11i11101 1000010b 8 + + + + + V 0 + a += J
add a,N 11000110 nnnnnnnn 7 + + + + + V 0 + a += N
add a,(hl) 10000110 7 + + + + + V 0 + a += (hl)
add a,(I+D) 11i11101 10000110 dddddddd 19 + + + + + V 0 + a += (I+D)
add hl,Q 00qq1001 11 - - + + + - 0 + hl += Q
add I,Q 11i11101 00qq1001 15 - - + + + - 0 + I += Q
and R 10100rrr 4 + + + 1 + P 0 0 a := a AND R
and J 11i11101 1010010b 8 + + + 1 + P 0 0 a := a AND J
and N 11100110 nnnnnnnn 7 + + + 1 + P 0 0 a := a AND N
and (hl) 10100110 7 + + + 1 + P 0 0 a := a AND (hl)
and (I+D) 11i11101 10100110 dddddddd 19 + + + 1 + P 0 0 a := a AND (I+D)
bit B,R 11001011 01bbbrrr 8 + + + 1 + P 0 - tmp := R AND [1 << B] => flags
bit B,(hl) 11001011 01bbb110 12 + +  ? 1  ? P 0 - tmp := (hl) AND [1 << B] => flags
bit B,(I+D) 11i11101 11001011 dddddddd 01bbb*** 20 + + X 1 X P 0 - tmp := (I+D) AND [1 << B] => flags,
xf := [I+D].13, yf := [I+D].11
call A 11001101 alalalal ahahahah 17 - - - - - - - - sp -= 2, (sp) := pc, pc := A
call C,A 11ccc100 alalalal ahahahah 17/10 - - - - - - - - if C then sp -= 2, (sp) := pc, pc := A
ccf 00111111 4 - - A X A - 0 X hf := cf, cf := ~cf
cp R 10111rrr 4 + + X + X V 1 + tmp := a - R => flags,
xf := R.5, yf = R.3
cp J 11i11101 1011110b 8 + + X + X V 1 + tmp := a - J => flags,
xf := J.5, yf = J.3
cp N 11111110 nnnnnnnn 7 + + X + X V 1 + tmp := a - N => flags,
xf := N.5, yf = N.3
cp (hl) 10111110 7 + + X + X V 1 + tmp := a - (hl) => flags,
xf := (hl).5, yf = (hl).3
cp (I+D) 11i11101 10111110 dddddddd 19 + + X + X V 1 + tmp := a - (I+D) => flags,
xf := (I+D).5, yf = (I+D).3
cpd 11101101 10101001 16 + + X + X X 1 - tmp := a - (hl) => flags,
bc -= 1, hl -= 1, pf := bc <> 0,
xf := [tmp - hf].1, yf = [tmp - hf].3
cpdr 11101101 10111001 21/16 + + X + X X 1 - cpd, if bc > 0 and nz then pc -= 2
cpi 11101101 10100001 16 + + X + X X 1 - tmp := a - (hl) => flags,
bc -= 1, hl += 1, pf := bc <> 0,
xf := [tmp - hf].1, yf = [tmp - hf].3
cpir 11101101 10110001 21/16 + + X + X X 1 - cpi, if bc > 0 and nz then pc -= 2
cpl 00101111 4 - - + 1 + - 1 - a := ~a
daa 00100111 4 + + + X + P - X tmp := a,
if nf then
 if hf or (a AND 0x0f > 9) then tmp -= 0x06
 if cf or (a > 0x99) then tmp -= 0x60
else
 if hf or (a AND 0x0f > 9) then tmp += 0x06
 if cf or (a > 0x99) then tmp += 0x60
endif,
tmp => flags, cf := cf OR (a > 0x99),
hf := a.4 XOR tmp.4, a := tmp
dec R 00rrr101 4 + + + + + V 1 - R -= 1
dec J 11i11101 0010b101 8 + + + + + V 1 - J -= 1
dec (hl) 00110101 11 + + + + + V 1 - (hl) -= 1
dec (I+D) 11i11101 00110101 dddddddd 19 + + + + + V 1 - (I+D) -= 1
dec Q 00qq1011 6 - - - - - - - - Q -= 1
dec I 11i11101 00101011 10 - - - - - - - - I -= 1
di 11110011 4 - - - - - - - - iff1 := 0, iff2 := 0
djnz E 00010000 dddddddd 13/8 - - - - - - - - b -= 1, if b <> 0 then pc := E
ei 11111011 4 - - - - - - - - iff1 := 1, iff2 := 1 after the next instruction
ex (sp),hl 11100011 19 - - - - - - - - (sp) <=> hl
ex (sp),I 11i11101 11100011 23 - - - - - - - - (sp) <=> I
ex af,af' 00001000 4 X X X X X X X X af <=> af'
ex de,hl 11101011 4 - - - - - - - - de <=> hl
exx 11011001 4 - - - - - - - - bc, de, hl <=> bc', de', hl'
halt 01110110 4 - - - - - - - - wait for interrupt
im 0 11101101 01000110 8 - - - - - - - - mode 0: execute instruction on bus
im 1 11101101 01010110 8 - - - - - - - - mode 1: execute rst $38
im 2 11101101 01011110 8 - - - - - - - - mode 2: call (i * 256 + byte on bus)
in a,(N) 11011011 nnnnnnnn 11 - - - - - - - - a := ((N))
in R,(c) 11101101 01rrr000 12 + + + 0 + P 0 - R := ((c))
in f,(c) 11101101 01110000 12 + + + 0 + P 0 - ((c)) => flags
inc R 00rrr100 4 + + + + + V 0 - R += 1
inc J 11i11101 0010b100 8 + + + + + V 0 - J += 1
inc (hl) 00110100 11 + + + + + V 0 - (hl) += 1
inc (I+D) 11i11101 00110100 dddddddd 23 + + + + + V 0 - (I+D) += 1
inc Q 00qq0011 6 - - - - - - - - Q += 1
inc I 11i11101 00100011 10 - - - - - - - - I += 1
ld R1,R2 01rrrsss 4 - - - - - - - - R1 := R2
pop P 11pp0001 10 - - - - - - - - P := (sp), sp += 2
push P 11pp0101 11 - - - - - - - - sp -= 2, (sp) := P
ret 11001001 10 - - - - - - - - pc := (sp), sp += 2

Legend

Notation Meaning Respective opcode bits
A 16-bit address alalalal ahahahah
B Bit number: 0..7 bbb = 000..111
C Condition: nz, z, nc, c, po, pe, p, m ccc = 000, 001, 010, 011, 100, 101, 110, 111
D 8-bit signed relative offset dddddddd
E 16-bit relative address dddddddd (E minus address of next instruction)
I Index register: ix, iy i = 0, 1
J Half index register: ixh, ixl, iyh, iyl (i, b) = (0, 0), (0, 1), (1, 0), (1, 1)
N 8-bit immediate nnnnnnnn
P 16-bit register pair: bc, de, hl, af pp = 00, 01, 10, 11
Q 16-bit register: bc, de, hl/ix/iy, sp qq = 00, 01, 10, 11
R 8-bit general purpose register: a, b, c, d, e, h, l rrr (or sss) = 111, 000, 001, 010, 011, 100, 101

Flags

  • - = no change
  • + = change by definition:
    • S = sign, bit 7 of the result byte (accumulator or high byte for 16-bit operations)
    • Z = zero, set if the result is zero (8 or 16-bit value)
    • X = undocumented, bit 5 of the result byte
    • H = half-carry, the carry (theoretical bit 4) of the low nibble of the result byte
    • Y = undocumented, bit 3 of the result byte
    • P = parity (set if the result byte has an even number of bits set) or overflow (set when crossing the boundary of the signed range); always specified
    • N = negative, set if the previous operation was a subtraction; always specified
    • C = carry, the theoretical bit 8 of the result byte
  • 0 = always reset
  • 1 = always set
  • X = change described under Effect
  • P = parity (only for the parity flag)
  • V = overflow (only for the parity flag)
  • A = OR with the respective bit of the accumulator

Miscellaneous

  • () = indirection
  • (()) = I/O port
  • [] = operator precedence (to avoid confusion with indirection)
  • E.B = the Bth bit of the value of expression E
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