Difference between revisions of "83Plus:Ports:55"
(Port 55 - active USB interrupts) |
Thepenguin77 (Talk | contribs) |
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[[Category:83Plus:Ports:By Address|55 - USB Interrupt State]] [[Category:83Plus:Ports:By Name|USB Interrupt State]] | [[Category:83Plus:Ports:By Address|55 - USB Interrupt State]] [[Category:83Plus:Ports:By Name|USB Interrupt State]] | ||
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== Synopsis == | == Synopsis == | ||
'''Port Number:''' 55h | '''Port Number:''' 55h | ||
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This port reports which USB interrupts have occurred. | This port reports which USB interrupts have occurred. | ||
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=== Read Values === | === Read Values === | ||
Revision as of 20:14, 27 October 2011
| This port only exists on the the TI-84 Plus and the TI-84 Plus Silver Edition. On the standard TI-83 Plus, it acts as a shadow of port 05. On the TI-83 Plus Silver Edition, this port has no effect. |
Synopsis
Port Number: 55h
Function: USB Interrupt State
This port reports which USB interrupts have occurred.
Read Values
- Bit 0: Normally set. Cleared for some (unknown, unusual) type of event.
- Bit 1: Normally set.
- Bit 2: Normally set. Cleared if a USB line interrupt has occurred.
- Bit 3: Normally set.
- Bit 4: Normally set. Cleared if a USB protocol interrupt has occurred.
- Bit 5: Always 0
- Bit 6: Always 0
- Bit 7: Always 0
Write Values
- No effect
Comments
Normally, the value of this port will be 1Fh. When a USB interrupt occurs, one or more of the bits will be cleared.
USB line interrupts are triggered when one of the four functional USB lines changes from low to high or high to low. Port 57 controls when these interrupts occur. When a line interrupt occurs, port 56 tells you which of the lines has changed. Use port 57 to acknowledge the interrupt.
USB protocol interrupts are triggered when (a) a USB device-level event occurs, such as a bus reset, or (b) a USB transaction finishes. Port 5B controls whether these interrupts occur. When one does, ports 82, 84, and 86 (and possibly 83 and 85) will tell you what event(s) caused the interrupt. Reading from any of these ports also clears it and acknowledges the interrupt.
Bit 0 indicates some other, and uncommon, type of event - possibly that the bus has been suspended. I think that this is also controlled by port 5B, and zeroing port 5B will acknowledge the interrupt. This should be tested.
