Difference between revisions of "83Plus:Ports:82"
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[[Category:83Plus:Ports:By Address|82 - USB Write-Pipe Events]] [[Category:83Plus:Ports:By Name|USB Write-Pipe Events]] | [[Category:83Plus:Ports:By Address|82 - USB Write-Pipe Events]] [[Category:83Plus:Ports:By Name|USB Write-Pipe Events]] | ||
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== Synopsis == | == Synopsis == | ||
'''Port Number:''' 82h | '''Port Number:''' 82h | ||
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This port reports when a USB transaction on a "write" pipe has finished. This port holds the values for ports A0h-A7h. Similar to [[83Plus:Ports:83|port 83]]. | This port reports when a USB transaction on a "write" pipe has finished. This port holds the values for ports A0h-A7h. Similar to [[83Plus:Ports:83|port 83]]. | ||
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=== Read Values === | === Read Values === | ||
Latest revision as of 20:17, 27 October 2011
| This port only exists on the the TI-84 Plus and the TI-84 Plus Silver Edition. On the standard TI-83 Plus, it acts as a shadow of port 02. On the TI-83 Plus Silver Edition, this port has no effect. |
Synopsis
Port Number: 82h
Function: USB Write-Pipe Events
This port reports when a USB transaction on a "write" pipe has finished. This port holds the values for ports A0h-A7h. Similar to port 83.
Read Values
Reading from this port also clears it. Remember the value you read, because you can't go back and read it again.
- Bit 0: Set if any transaction (read or write) has finished on pipe 0.
- Bit 1: Set if a write transaction has finished on pipe 1.
- Bit 2: Set if a write transaction has finished on pipe 2.
- Bit 3: Set if a write transaction has finished on pipe 3.
- Bit 4: Hypothetically, set if a write transaction has finished on pipe 4.
- Bit 5: Hypothetically, set if a write transaction has finished on pipe 5.
- Bit 6: Hypothetically, set if a write transaction has finished on pipe 6.
- Bit 7: Hypothetically, set if a write transaction has finished on pipe 7.
Write Values
- No effect
Comments
This port is used to report the status of port-91 USB transactions. Note that this port only works if port 5B bit 0 is set. Port 87 might also act as a mask for this port.
After you write a command to port 91, the USB controller will attempt to perform the appropriate transaction for you. This may, of course, take some time (if the calculator is the host, you must wait for the peripheral to respond; if the calculator is the peripheral, you must wait for the host to ask you to speak.) If the calculator is host and the peripheral isn't ready (it sends a NAK), the controller will need to re-try the transaction, possibly several times. When the transaction actually finishes, a Z80 interrupt will be generated and the appropriate bit of this port will be set.
As a host, control, bulk, and interrupt transactions are considered to have "finished" when the peripheral device has either sent an ACK (indicating the packet was received successfully), sent a STALL (indicating an error condition), or failed to reply. Which of the these has occurred can be determined from port 91 (with port 8E set appropriately.)
As a peripheral, the transaction is considered to have "finished" when the host has requested, received, and acknowledged the data packet, or the host has requested a data packet and the calculator has replied with a STALL.
For some bizarre reason, port 91 is also used for IN (as well as OUT/SETUP) control transactions as host, and OUT/SETUP (as well as IN) control transactions as peripheral. In these cases, port 82 bit 0 is set, and port 96 (with port 8E set to 0) tells you how many bytes were received.
Port-94 transactions (i.e., iso/bulk/interrupt IN transactions as host, and OUT transactions as peripheral) are associated with port 84.
Isochronous transactions haven't been tested, and probably behave somewhat differently.
