Difference between revisions of "84PCE:Ports:7000"

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(Updated with full documentation)
(Do we like tables? I like tables, leave a comment if you don't.)
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== Registers ==
 
== Registers ==
 
All registers are little-endian and cross multiple 8-bit ports.
 
All registers are little-endian and cross multiple 8-bit ports.
−
* Timers 1, 2, 3:
+
 
−
** 7000, 7010, 7020 (R/W):
+
{|-
−
*** 32-bit counter register. Can be written directly, but it should be disabled first since the entire value cannot be written atomically.
+
|<u>Timer 1</u>&nbsp;&nbsp;&nbsp;
−
** 7004, 7014, 7024 (R/W):
+
|<u>Timer 2</u>&nbsp;&nbsp;&nbsp;
−
*** 32-bit reload register. The counter is reloaded with this value once it reaches 0.
+
|<u>Timer 3</u>&nbsp;&nbsp;&nbsp;
−
** 7008, 7018, 7028 (R/W):
+
|<u>Bits, R/W?</u>&nbsp;&nbsp;&nbsp;
−
*** 32-bit match register 1. An interrupt will be generated when the counter matches this value.
+
|<u>Purpose</u>&nbsp;&nbsp;&nbsp;
−
** 700C, 701C, 702C (R/W):
+
|<u>Description</u>&nbsp;&nbsp;&nbsp;
−
*** 32-bit match register 2. An interrupt will be generated when the counter matches this value.
+
|-
−
** 7030 (R/W): 12-bit control register.
+
|7000<br/>F20000
−
*** Bits 0,3,6: Timer enable. Set to enable the corresponding timer.
+
|7010<br/>F20010
−
*** Bits 1,4,7: Clock source. Set to 1 to use the 32768Hz clock, or 0 to use the CPU clock.
+
|7020<br/>F20020
−
*** Bits 2,5,8: Overflow interrupt enable. Set to generate an interrupt when the counter reaches 0.
+
|32-bit<br/>R/W
−
*** Bits 9,10,11: Count direction. Set to 1 to count up, or 0 to count down.
+
|Counter register&nbsp;&nbsp;&nbsp;
−
** 7034 (R/W): 12-bit interrupt status register. Reads the cause of the interrupt. Write 1 bits to reset.
+
|Can be written directly, but it should be disabled first since the entire value cannot be written atomically.
−
*** Bits 0,3,6: Match 1. Set after the counter reaches match register 1.
+
|-
−
*** Bits 1,4,7: Match 2. Set after the counter reaches match register 2.
+
|7004<br/>F20004
−
*** Bits 2,5,8: Overflow. Set after the counter reaches 0 and gets reloaded, but only if enabled in the control register.
+
|7014<br/>F20014
−
** 7038 (R/W): 12-bit interrupt mask? Seems to have no effect on interrupt generation, however.
+
|7014<br/>F20024
−
** 703C (R):
+
|32-bit<br/>R/W
−
*** 32-bit revision register. Reads a constant 0x00010801, which corresponds to revision 1.8.1.
+
|Reset value&nbsp;&nbsp;&nbsp;
 +
|The counter is reloaded with this value once it reaches 0.
 +
|-
 +
|7008<br/>F20008
 +
|7018<br/>F20018
 +
|7018<br/>F20028
 +
|32-bit<br/>R/W
 +
|Match value 1&nbsp;&nbsp;&nbsp;
 +
|An interrupt will be generated when the counter matches this value.
 +
|-
 +
|700C<br/>F2000C
 +
|701C<br/>F2001C
 +
|701C<br/>F2002C
 +
|32-bit<br/>R/W
 +
|Match value 2&nbsp;&nbsp;&nbsp;
 +
|An interrupt will be generated when the counter matches this value.
 +
|-
 +
|7030<br/>F20030
 +
|<i>Same</i>
 +
|<i>Same</i>
 +
|12-bit<br/>R/W
 +
|Control register
 +
|-
 +
|&nbsp;&bull; Bit 0
 +
|&nbsp;&bull; Bit 3
 +
|&nbsp;&bull; Bit 6
 +
|
 +
|Timer enable
 +
|Set to enable the corresponding timer.
 +
|-
 +
|&nbsp;&bull; Bit 1
 +
|&nbsp;&bull; Bit 4
 +
|&nbsp;&bull; Bit 7
 +
|
 +
|Clock source
 +
|Set 1 for 32768&nbsp;Hz crystal, or 0 for CPU clock
 +
|-
 +
|&nbsp;&bull; Bit 2
 +
|&nbsp;&bull; Bit 5
 +
|&nbsp;&bull; Bit 8
 +
|
 +
|Interrupt enable&nbsp;&nbsp;&nbsp;
 +
|Set to generate an interrupt when the counter reaches 0.
 +
|-
 +
|&nbsp;&bull; Bit 9
 +
|&nbsp;&bull; Bit 10
 +
|&nbsp;&bull; Bit 11
 +
|
 +
|Count direction&nbsp;&nbsp;&nbsp;
 +
|Set to 1 to count up, or 0 to count down.
 +
|-
 +
|7034<br/>F20034
 +
|<i>Same</i>
 +
|<i>Same</i>
 +
|12-bit<br/>R/W
 +
|Interrupt status
 +
|Reads the cause of the interrupt. Write 1 bits to reset.
 +
|-
 +
|&nbsp;&bull; Bit 0
 +
|&nbsp;&bull; Bit 3
 +
|&nbsp;&bull; Bit 6
 +
|
 +
|Match 1&nbsp;&nbsp;&nbsp;
 +
|Set after the counter reaches match register 1.
 +
|-
 +
|&nbsp;&bull; Bit 1
 +
|&nbsp;&bull; Bit 4
 +
|&nbsp;&bull; Bit 7
 +
|
 +
|Match 2&nbsp;&nbsp;&nbsp;
 +
|Set after the counter reaches match register 2.
 +
|-
 +
|&nbsp;&bull; Bit 2
 +
|&nbsp;&bull; Bit 5
 +
|&nbsp;&bull; Bit 8
 +
|
 +
|Overflow&nbsp;&nbsp;&nbsp;
 +
|Set after the counter reaches 0 and gets reloaded, but only if enabled in the control register.
 +
|-
 +
|7038<br/>F20038
 +
|<i>Same</i>
 +
|<i>Same</i>
 +
|12-bit<br/>R/W
 +
|Interrupt mask?
 +
|Seems to have no effect on interrupt generation, despite being documented
 +
|-
 +
|7038<br/>F20038
 +
|
 +
|
 +
|32-bit<br/>R
 +
|Revision number
 +
|Reads a constant 0x00010801, which corresponds to revision 1.8.1.
 +
|}

Revision as of 09:04, 4 April 2015

Synopsis

Port Number: 7000-703F

Memory-mapped address: F20000

Function: General-Purpose Timers

This range provides three general-purpose 32-bit timers (appears to be model FTTMR010). They can count up or down, and run at either 32768Hz or the CPU clock speed. The counters can generate interrupts either when looping or when matching one of two customizable values. The OS uses the third timer when USB is connected.

Registers

All registers are little-endian and cross multiple 8-bit ports.

Timer 1    Timer 2    Timer 3    Bits, R/W?    Purpose    Description   
7000
F20000 		7010
F20010 		7020
F20020 		32-bit
R/W 		Counter register    Can be written directly, but it should be disabled first since the entire value cannot be written atomically.
7004
F20004 		7014
F20014 		7014
F20024 		32-bit
R/W 		Reset value    The counter is reloaded with this value once it reaches 0.
7008
F20008 		7018
F20018 		7018
F20028 		32-bit
R/W 		Match value 1    An interrupt will be generated when the counter matches this value.
700C
F2000C 		701C
F2001C 		701C
F2002C 		32-bit
R/W 		Match value 2    An interrupt will be generated when the counter matches this value.
7030
F20030 		Same Same 12-bit
R/W 		Control register
 • Bit 0  • Bit 3  • Bit 6 Timer enable Set to enable the corresponding timer.
 • Bit 1  • Bit 4  • Bit 7 Clock source Set 1 for 32768 Hz crystal, or 0 for CPU clock
 • Bit 2  • Bit 5  • Bit 8 Interrupt enable    Set to generate an interrupt when the counter reaches 0.
 • Bit 9  • Bit 10  • Bit 11 Count direction    Set to 1 to count up, or 0 to count down.
7034
F20034 		Same Same 12-bit
R/W 		Interrupt status Reads the cause of the interrupt. Write 1 bits to reset.
 • Bit 0  • Bit 3  • Bit 6 Match 1    Set after the counter reaches match register 1.
 • Bit 1  • Bit 4  • Bit 7 Match 2    Set after the counter reaches match register 2.
 • Bit 2  • Bit 5  • Bit 8 Overflow    Set after the counter reaches 0 and gets reloaded, but only if enabled in the control register.
7038
F20038 		Same Same 12-bit
R/W 		Interrupt mask? Seems to have no effect on interrupt generation, despite being documented
7038
F20038 		32-bit
R 		Revision number Reads a constant 0x00010801, which corresponds to revision 1.8.1.
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