Difference between revisions of "84PCE:Ports:0000 Unknowns"
From WikiTI
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|03 | |03 | ||
|03? | |03? | ||
| − | | | + | |Display refresh |
|- | |- | ||
|[[:84PCE:Ports:0007|0007]] | |[[:84PCE:Ports:0007|0007]] | ||
Revision as of 02:39, 6 August 2017
If a port is not listed; it indicates that writes have no effect and do not latch, and that reads are 0. Note that this may not be true one hundred percent.
0000 Range
| Port | Default | Bits | Information |
| 0000 | 03 | D3 | CPU Speed Control |
| 0001 | 03 | 13 | OS Timer Control |
| 0002 | ?? | Read only, value can change | |
| 0005 | 76 | ?? | Set bit 5 to freeze, bit 6 affects backlight |
| 0006 | 03 | 03? | Display refresh |
| 0007 | B7 | FF | Reset bit 1 to cause crash after ? 1 second |
| 0008 | 7F | ?? | Cannot change value |
| 0009 | ?? | Appears to be a part of the power control system. | |
| 000A | 05 | ?? | Latches value written, OS reset to 05 |
| 000B | FC | ?? | Cannot change value |
| 000C | 00 | FF | Latches value written |
| 000D | FF | FF | Bit 0: Freeze if reset Bit 1: Crash if reset Bit 2: No apparent effect if reset Bit 3: Reset to disable VRAM? Upon set, VRAM is garbage. Bits [7:4]Possibly last value written |
| 000E | 0A | FF | Latches value written |
| 000F | 42 | ?3 | High nibble may be a status, low 2 bits latch value written |
| 001C | 80 | ?? | Cannot change value |
| 0028 | FD | Bit 1 is always 0, other bits latch value written | |
| 0029 | 00 | 01 | Bit 0 latches value written |
| 002A | 70 | 73 | Latches value written |
| 002B | FE | FF | Latches value written |
| 002C | FF | Ports 002C-0031 latch value written | |
| 0032 | 07 | Latches value written | |
| 0033 | F1 | Latches value written | |
| 0034 | 31 | Latches value written | |
| 0035 | 3F | Latches value written | |
| 0036 | FF | Ports 0036-0039 latch value written |
