Difference between revisions of "84PCE:Ports:0006"
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(Updated effect of bits 0 & 1 on port access) |
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=== Bit [0] === | === Bit [0] === | ||
| − | Latches value written, OS defaults this to set. Resetting this bit reduces current consumption by about 3 mA, so it does ''something.'' | + | Latches value written, OS defaults this to set. Resetting this bit reduces current consumption by about 3 mA, so it does ''something.'' When reset, the [[84PCE:Ports:3000|USB controller ports]] cannot be written & read as 20 0E 3E 00, repeating every 4 bytes. |
=== Bit [1] === | === Bit [1] === | ||
| − | Reset this bit to disable display upadates. | + | Reset this bit to disable display upadates. When reset, the [[84PCE:Ports:4000|LCD controller ports]] cannot be written & read as B1 00 00 00 (revision C) or 2D 09 00 00 (revision N), repeating every 4 bytes. |
=== Bit [2] === | === Bit [2] === | ||
Revision as of 21:40, 20 February 2021
Contents
Synopsis
Port Number: 0006
Function: Unknown
Details
This port seems to affect the display refresh.
Bit [0]
Latches value written, OS defaults this to set. Resetting this bit reduces current consumption by about 3 mA, so it does something. When reset, the USB controller ports cannot be written & read as 20 0E 3E 00, repeating every 4 bytes.
Bit [1]
Reset this bit to disable display upadates. When reset, the LCD controller ports cannot be written & read as B1 00 00 00 (revision C) or 2D 09 00 00 (revision N), repeating every 4 bytes.
Bit [2]
Set this bit to enable display updates if bit 1 is ever reset. ???
This bit is known to unlock protected ports, such as SHA256, and enables the flash unlock sequence. It is cleared every time the boot code interrupt handler runs.
Bit [3]
Writes do not latch; no apparent effect.
Used by OS on Python Edition.
Bit [4]
Flash lock status.
Bits [7:3]
Writes do not latch; no apparent effect.
