Difference between revisions of "84PCE:Ports:8000"

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(Document load status register, update terminology and details)
 
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== Registers ==
 
== Registers ==
−
* Count registers:
+
* Latched registers (copied from the internal counters once per second):
−
** 8000 (R): Current second count (from 00h to 3Bh, or 0-59 decimal).
+
** 8000 (R): Latched second count (from 00h to 3Bh, or 0-59 decimal).
−
** 8004 (R): Current minute count (from 00h to 3Bh, or 0-59 decimal).
+
** 8004 (R): Latched minute count (from 00h to 3Bh, or 0-59 decimal).
−
** 8008 (R): Current hour count (from 00h to 17h, or 0-23 decimal).
+
** 8008 (R): Latched hour count (from 00h to 17h, or 0-23 decimal).
−
** 800C-800D (R): Current day count (16-bit little-endian).
+
** 800C-800D (R): Latched day count (16-bit little-endian).
 
* Alarm registers:
 
* Alarm registers:
 
** 8010 (R/W): Alarm second value.
 
** 8010 (R/W): Alarm second value.
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** 8018 (R/W): Alarm hour value.
 
** 8018 (R/W): Alarm hour value.
 
* 8020 (R/W): Control register.
 
* 8020 (R/W): Control register.
−
** Bit 0: Set to enable the RTC.
+
** Bit 0: Set to enable ticking the internal counters.
 
** Bit 1: Set to enable second interrupt.
 
** Bit 1: Set to enable second interrupt.
 
** Bit 2: Set to enable minute interrupt.
 
** Bit 2: Set to enable minute interrupt.
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** Bit 4: Set to enable day interrupt.
 
** Bit 4: Set to enable day interrupt.
 
** Bit 5: Set to enable alarm interrupt.
 
** Bit 5: Set to enable alarm interrupt.
−
** Bit 6: Load operation. Write a 1 to load the Count registers with the values in the Write registers. When the load operation completes, the bit will return to 0.
+
** Bit 6: Load operation. Write a 1 to load both the internal counters and the Latched registers (ignoring the Latch enable bit) with the values in the Load registers. When the load operation fully completes, the bit will return to 0. Writing to this bit while it reads 1 has no effect.
−
** Bit 7: Reset to freeze the count registers. The time will continue to advance internally. Once this bit is set again, the count registers will not be updated to the current time until the next second tick.
+
** Bit 7: Latch enable. Reset to disable latching the internal counters into the Latched registers. The internal counters will continue to advance. Once this bit is set again, the Latched registers will not be updated to the current time until the next second tick.
−
* Write registers:
+
* Load registers:
−
** 8024 (R/W): Write second register.
+
** 8024 (R/W): Load second register.
−
** 8028 (R/W): Write minute register.
+
** 8028 (R/W): Load minute register.
−
** 802C (R/W): Write hour register.
+
** 802C (R/W): Load hour register.
−
** 8030-8031 (R/W): Write day register.
+
** 8030-8031 (R/W): Load day register.
 
* 8034 (R/W): Interrupt status register. Reads the cause of the interrupt. Write 1 bits to reset. '''If any bits are set, they will continuously generate interrupts until acknowledged'''
 
* 8034 (R/W): Interrupt status register. Reads the cause of the interrupt. Write 1 bits to reset. '''If any bits are set, they will continuously generate interrupts until acknowledged'''
 
** Bit 0: Second interrupt.
 
** Bit 0: Second interrupt.
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** Bit 3: Day interrupt.
 
** Bit 3: Day interrupt.
 
** Bit 4: Alarm interrupt.
 
** Bit 4: Alarm interrupt.
−
** Bit 5: Load operation complete
+
** Bit 5: Load operation to Latched registers complete. The internal counters take longer to load, see the Load status register.
 
* 803C-803F (R): Revision register. Reads 0x00010500 for revision 1.5.0.
 
* 803C-803F (R): Revision register. Reads 0x00010500 for revision 1.5.0.
−
* 8044-8047 (R): Groups up all the time values into 32 bits (little-endian). Not very useful on the eZ80 which cannot load it atomically.
+
* 8040 (R): Load status register. Each bit is set to 1 if the Load register has not been fully loaded into the corresponding internal counter yet, or 0 if the Load register can be safely written.
−
** Bits 0-5: Current second count.
+
** Bit 3: Unknown, remains 1 for around 300 microseconds after the Control register indicates load completion.
−
** Bits 6-11: Current minute count.
+
** Bit 4: Load second status.
−
** Bits 12-16: Current hour count.
+
** Bit 5: Load minute status.
−
** Bit 17-31: Low 15 bits of current day count.
+
** Bit 6: Load hour status.
 +
** Bit 7: Load day status.
 +
* 8044-8047 (R): Groups up all the latched time values into 32 bits (little-endian). Not very useful on the eZ80 which cannot load it atomically.
 +
** Bits 0-5: Latched second count.
 +
** Bits 6-11: Latched minute count.
 +
** Bits 12-16: Latched hour count.
 +
** Bit 17-31: Low 15 bits of latched day count.

Latest revision as of 00:10, 23 September 2024


The RTC is similar to the FTRTC010 or the FTRTC011. It has separate second/minute/hour/day counters, and can trigger an interrupt when any of the counters changes or when the current time of day matches an alarm value.

Synopsis

Port Number: 8000

Memory-mapped address: F30000

Function: Real-Time Clock

Registers

  • Latched registers (copied from the internal counters once per second):
    • 8000 (R): Latched second count (from 00h to 3Bh, or 0-59 decimal).
    • 8004 (R): Latched minute count (from 00h to 3Bh, or 0-59 decimal).
    • 8008 (R): Latched hour count (from 00h to 17h, or 0-23 decimal).
    • 800C-800D (R): Latched day count (16-bit little-endian).
  • Alarm registers:
    • 8010 (R/W): Alarm second value.
    • 8014 (R/W): Alarm minute value.
    • 8018 (R/W): Alarm hour value.
  • 8020 (R/W): Control register.
    • Bit 0: Set to enable ticking the internal counters.
    • Bit 1: Set to enable second interrupt.
    • Bit 2: Set to enable minute interrupt.
    • Bit 3: Set to enable hour interrupt.
    • Bit 4: Set to enable day interrupt.
    • Bit 5: Set to enable alarm interrupt.
    • Bit 6: Load operation. Write a 1 to load both the internal counters and the Latched registers (ignoring the Latch enable bit) with the values in the Load registers. When the load operation fully completes, the bit will return to 0. Writing to this bit while it reads 1 has no effect.
    • Bit 7: Latch enable. Reset to disable latching the internal counters into the Latched registers. The internal counters will continue to advance. Once this bit is set again, the Latched registers will not be updated to the current time until the next second tick.
  • Load registers:
    • 8024 (R/W): Load second register.
    • 8028 (R/W): Load minute register.
    • 802C (R/W): Load hour register.
    • 8030-8031 (R/W): Load day register.
  • 8034 (R/W): Interrupt status register. Reads the cause of the interrupt. Write 1 bits to reset. If any bits are set, they will continuously generate interrupts until acknowledged
    • Bit 0: Second interrupt.
    • Bit 1: Minute interrupt.
    • Bit 2: Hour interrupt.
    • Bit 3: Day interrupt.
    • Bit 4: Alarm interrupt.
    • Bit 5: Load operation to Latched registers complete. The internal counters take longer to load, see the Load status register.
  • 803C-803F (R): Revision register. Reads 0x00010500 for revision 1.5.0.
  • 8040 (R): Load status register. Each bit is set to 1 if the Load register has not been fully loaded into the corresponding internal counter yet, or 0 if the Load register can be safely written.
    • Bit 3: Unknown, remains 1 for around 300 microseconds after the Control register indicates load completion.
    • Bit 4: Load second status.
    • Bit 5: Load minute status.
    • Bit 6: Load hour status.
    • Bit 7: Load day status.
  • 8044-8047 (R): Groups up all the latched time values into 32 bits (little-endian). Not very useful on the eZ80 which cannot load it atomically.
    • Bits 0-5: Latched second count.
    • Bits 6-11: Latched minute count.
    • Bits 12-16: Latched hour count.
    • Bit 17-31: Low 15 bits of latched day count.
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