Difference between revisions of "User:CoBB"

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(→‎Z80 instruction set)
(→‎Z80 instruction set)
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|-
 
|-
 
| add iy,Q || <tt>11111101 00qq1001</tt> || 15 || - || - || + || + || + || - || 0 || + || iy += Q
 
| add iy,Q || <tt>11111101 00qq1001</tt> || 15 || - || - || + || + || + || - || 0 || + || iy += Q
 +
|-
 +
| and R || <tt>10100rrr</tt> || 4 || + || + || + || 1 || + || P || 0 || 0 || a := a AND R
 +
|-
 +
| and N || <tt>11100110 nnnnnnnn</tt> || 7 || + || + || + || 1 || + || P || 0 || 0 || a := a AND N
 +
|-
 +
| and (hl) || <tt>10100110</tt> || 7 || + || + || + || 1 || + || P || 0 || 0 || a := a AND (hl)
 +
|-
 +
| and (ix+D) || <tt>11011101 10100110 dddddddd</tt> || 19 || + || + || + || 1 || + || P || 0 || 0 || a := a AND (ix+D)
 +
|-
 +
| and (iy+D) || <tt>11111101 10100110 dddddddd</tt> || 19 || + || + || + || 1 || + || P || 0 || 0 || a := a AND (iy+D)
 +
|-
 +
| bit B,R || <tt>01bbbrrr</tt> || 8 || + || + || + || 1 || + || P || 0 || - || tmp := R AND [1 << B] => flags
 +
|-
 +
| bit B,(hl) || <tt>01bbb110</tt> || 12 || + || + || ? || 1 || ? || P || 0 || - || tmp := (hl) AND [1 << B] => flags
 +
|-
 +
| bit B,(ix+D) || <tt>11011101 01bbb110 dddddddd</tt> || 20 || + || + || X || 1 || X || P || 0 || - || tmp := (ix+D) AND [1 << B] => flags,<br>xf := [ix+D].13, yf := [ix+D].11
 +
|-
 +
| bit B,(iy+D) || <tt>11111101 01bbb110 dddddddd</tt> || 20 || + || + || X || 1 || X || P || 0 || - || tmp := (iy+D) AND [1 << B] => flags,<br>xf := [iy+D].13, yf := [iy+D].11
 
|-
 
|-
 
| call A || <tt>11001101 alalalal ahahahah</tt> || 17 || - || - || - || - || - || - || - || - || sp -= 2, (sp) := pc, pc := A
 
| call A || <tt>11001101 alalalal ahahahah</tt> || 17 || - || - || - || - || - || - || - || - || sp -= 2, (sp) := pc, pc := A
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|-
 
|-
 
| A || 16-bit address || alalalal ahahahah
 
| A || 16-bit address || alalalal ahahahah
 +
|-
 +
| B || Bit number: 0..7 || bbb = 000..111
 
|-
 
|-
 
| D || 8-bit signed relative offset || dddddddd
 
| D || 8-bit signed relative offset || dddddddd
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| P || 16-bit register pair: bc, de, hl, af || pp = 00, 01, 10, 11
 
| P || 16-bit register pair: bc, de, hl, af || pp = 00, 01, 10, 11
 
|-
 
|-
−
| Q || 16-bit register: bc, de, hl, sp || qq = 00, 01, 10, 11
+
| Q || 16-bit register: bc, de, hl/ix/iy, sp || qq = 00, 01, 10, 11
 
|-
 
|-
 
| R || 8-bit general purpose register: a, b, c, d, e, h, l || rrr (or sss) = 111, 000, 001, 010, 011, 100, 101
 
| R || 8-bit general purpose register: a, b, c, d, e, h, l || rrr (or sss) = 111, 000, 001, 010, 011, 100, 101
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* V = overflow (only for the parity flag)
 
* V = overflow (only for the parity flag)
 
* A = OR with the respective bit of the accumulator
 
* A = OR with the respective bit of the accumulator
 +
 +
=== Miscellaneous ===
 +
 +
* () = indirection
 +
* [] = operator precedence (to avoid confusion with indirection)
 +
* E.B = the Bth bit of the value of expression E

Revision as of 14:16, 26 February 2006

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Z80 instruction set

Reference

Instruction Opcode Time S Z X H Y P N C Effect
adc a,R 10001rrr 4 + + + + + V 0 + a += R + cf
adc a,N 11001110 nnnnnnnn 7 + + + + + V 0 + a += N + cf
adc a,(hl) 10001110 7 + + + + + V 0 + a += (hl) + cf
adc a,(ix+D) 11011101 10001110 dddddddd 19 + + + + + V 0 + a += (ix+D) + cf
adc a,(iy+D) 11111101 10001110 dddddddd 19 + + + + + V 0 + a += (iy+D) + cf
adc hl,Q 11101101 01qq1010 15 + + + + + V 0 + hl += Q + cf
add a,R 10000rrr 4 + + + + + V 0 + a += R
add a,N 11000110 nnnnnnnn 7 + + + + + V 0 + a += N
add a,(hl) 10000110 7 + + + + + V 0 + a += (hl)
add a,(ix+D) 11011101 10000110 dddddddd 19 + + + + + V 0 + a += (ix+D)
add a,(iy+D) 11111101 10000110 dddddddd 19 + + + + + V 0 + a += (iy+D)
add hl,Q 00qq1001 11 - - + + + - 0 + hl += Q
add ix,Q 11011101 00qq1001 15 - - + + + - 0 + ix += Q
add iy,Q 11111101 00qq1001 15 - - + + + - 0 + iy += Q
and R 10100rrr 4 + + + 1 + P 0 0 a := a AND R
and N 11100110 nnnnnnnn 7 + + + 1 + P 0 0 a := a AND N
and (hl) 10100110 7 + + + 1 + P 0 0 a := a AND (hl)
and (ix+D) 11011101 10100110 dddddddd 19 + + + 1 + P 0 0 a := a AND (ix+D)
and (iy+D) 11111101 10100110 dddddddd 19 + + + 1 + P 0 0 a := a AND (iy+D)
bit B,R 01bbbrrr 8 + + + 1 + P 0 - tmp := R AND [1 << B] => flags
bit B,(hl) 01bbb110 12 + +  ? 1  ? P 0 - tmp := (hl) AND [1 << B] => flags
bit B,(ix+D) 11011101 01bbb110 dddddddd 20 + + X 1 X P 0 - tmp := (ix+D) AND [1 << B] => flags,
xf := [ix+D].13, yf := [ix+D].11
bit B,(iy+D) 11111101 01bbb110 dddddddd 20 + + X 1 X P 0 - tmp := (iy+D) AND [1 << B] => flags,
xf := [iy+D].13, yf := [iy+D].11
call A 11001101 alalalal ahahahah 17 - - - - - - - - sp -= 2, (sp) := pc, pc := A
ccf 00111111 4 - - A X A - 0 X hf := cf, cf := ~cf
ld R1,R2 01rrrsss 4 - - - - - - - - R1 := R2
pop P 11pp0001 10 - - - - - - - - P := (sp), sp += 2
push P 11pp0101 11 - - - - - - - - sp -= 2, (sp) := P
ret 11001001 10 - - - - - - - - pc := (sp), sp += 2

Legend

Notation Meaning Respective opcode bits
A 16-bit address alalalal ahahahah
B Bit number: 0..7 bbb = 000..111
D 8-bit signed relative offset dddddddd
N 8-bit immediate nnnnnnnn
P 16-bit register pair: bc, de, hl, af pp = 00, 01, 10, 11
Q 16-bit register: bc, de, hl/ix/iy, sp qq = 00, 01, 10, 11
R 8-bit general purpose register: a, b, c, d, e, h, l rrr (or sss) = 111, 000, 001, 010, 011, 100, 101

Flags

  • - = no change
  • + = change by definition:
    • S = sign, bit 7 of the result byte (accumulator or high byte for 16-bit operations)
    • Z = zero, set if the result is zero (8 or 16-bit value)
    • X = undocumented, bit 5 of the result byte
    • H = half-carry, the carry of the low nibble of the result byte
    • Y = undocumented, bit 3 of the result byte
    • P = parity (set if the result byte has an even number of bits set) or overflow (set when crossing the boundary of the signed range); always specified
    • N = negative, set if the previous operation was a subtraction; always specified
    • C = carry, the theoretical bit 8 of the result byte
  • 0 = always reset
  • 1 = always set
  • X = change described under Effect
  • P = parity (only for the parity flag)
  • V = overflow (only for the parity flag)
  • A = OR with the respective bit of the accumulator

Miscellaneous

  • () = indirection
  • [] = operator precedence (to avoid confusion with indirection)
  • E.B = the Bth bit of the value of expression E
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