84PCE:Ports:A000

Synopsis

Port Number: A000-?

Memory-mapped address: F50000-?

Function: Set the mode of the keypad controller

The CE appears to use the same keypad controller as the nSpire.

• F50000 (R/W):
  • Bits 0-1: Scan mode
    • Mode 0: Idle.
    • Mode 1: Indiscriminate key detection. Data registers are not updated, but whenever any key is pressed, interrupt bit 2 is set (and cannot be cleared until the key is released).
    • Mode 2: Single scan. The keypad is scanned once, and then the mode returns to 0.
    • Mode 3: Continuous scan. When scanning completes, it just starts over again after a delay.
  • Bits 2-15: Number of APB cycles to wait before scanning each row
  • Bits 16-31: Number of APB cycles to wait between scans

• F50004 (R/W):
  • Bits 0-7: Number of rows to read (later rows are not updated in F50010-F5002F, and just read as whatever they were before being disabled)
  • Bits 8-15: Number of columns to read (later column bits in a row are set to 1 when it is updated)
• F50008 (R/W): Keypad interrupt status/acknowledge (3-bit). Write "1" bits to acknowledge.
  • Bit 0: Keypad scan complete
  • Bit 1: Keypad data register changed
  • Bit 2: Key pressed in mode 1

• F5000C (R/W): Keypad interrupt mask (3-bit). Set each bit to 1 if the corresponding event in [F50008] should cause an interrupt.

• F50010-F5002F (R): Keypad data, one halfword per row.

• F50030-F5003F (R/W): Keypad GPIOs. Each register is 20 bits, with one bit per GPIO. The role of each register is unknown.

TI executes this to set up the timings of the keypad:

 ld bc,0F50000h
 xor a
 ld (bc),a
 inc c
 ld a,15
 ld (bc),a
 inc c
 xor a
 ld (bc),a
 inc c
 ld a,15
 ld (bc),a
 inc c
 ld a,8
 ld (bc),a
 inc c
 ld (bc),a	; Read 8 rows; even though there is only 7 needed?