84PCE:Ports:1000
From WikiTI
Some of these ports have something to do with flash wait states, but no effect on RAM wait states has been observed. At the moment, it seems TI decided to design hardware with a fixed 4-cycle wait on RAM accesses. And it's probably SRAM.
| Port | Default | Bits | Information |
| 1000 | 01 | 01 | Reset bit 0 to crash. Affects flash wait states. |
| 1001 | 00 | ?? | Freeze if write value greater than 3F |
| 1002 | 06 | 0F | Possibly flash wait states, needs confirmation |
| 1003 | 00 | FF | Latches value written |
| 1004 | 00 | FF | Latches value written |
| 1005 | 00 | ?? | Primary flash wait state control |
| 1006 | 00 | FF | Latches value written |
| 1007 | FF | FF | Latches value written |
| 1008 | 00 | 01 | Latches value written |
| 1009 | 00 | FF | Latches value written |
| 100A | 00 | 0F | Latches value written |
| 100B | 00 | FF | Ports 100B-100F latch value written |
| 1010 | 00 | 01 | Latches value written |
| 1011 | 00 | FF | Latches value written |
| 1012 | 00 | 0F | Latches value written |
| 1013 | 00 | FF | Ports 1013-1017 latch value written |
