84PCE:LCD Controller

The CE contains two LCD controllers which work in tandem. This page primarily focuses on the one directly driving the LCD, the Sitronix ST7789.

See also the Primecell PL111 which drives the RGB interface, and the SPI Controller which provides the command interface.

Quick Specs

• Sitronix ST7789 family LCD controller
• TFT color LCD
• Supports RGB and SPI interfaces
• 172,800 bytes internal RAM
• 76,800 pixels (240x320 resolution)
• Power-saving 8-color mode
• 262,144 = 2^18 = 6x6x6 colors
• Data sheet: https://www.rhydolabz.com/documents/33/ST7789.pdf
• Physical LCD: Giant GPM1421C0

Overview

The LCD is a 240x320 pixel display rotated 90 degrees. To make terminology consistent, directions will be described relative to the CE itself, not relative to the display. As such, each scanline appears in a vertical orientation and the display is scanned from left to right. Note that the datasheet will not agree with this page when it comes to the terms "row" and "column". When appropriate, columns (which correspond to scanlines) will be referred to as "lines" to be more consistent with the datasheet.

Operating modes

The controller operates in one of three modes, dictating the refresh rate and scan timing:

RGB Interface

In this mode, the controller accepts the following signals from the Primecell PL111:

• Frame synchronization pulse (CLFP)
• Line synchronization pulse (CLLP)
• Pixel clock (CLCP)
• RGB pixel data (CLD)
• Data enable (CLAC)

This is TI's default setting, and causes the scan timing to be completely controlled by the Primecell.

To prevent scan errors, the Primecell must be configured with at least 240 pixel clocks per line and at least 320 lines per frame, plus the back porch values configured in RGB Interface Control. Note that these pixel clocks and lines are not required to be during active video of the Primecell, as it drives the pixel clock and line sync pulses even during porches.

Active video on the Primecell will drive the data enable and RGB pixel data signals, which are accepted by the RGB interface and written to display RAM, if enabled.

The RGB interface may also be configured with the WO bit of RGB Interface Control to bypass display RAM entirely and output the RGB pixel data signals directly to the display. Of course, this requires precisely a 240x320 active video configuration on the Primecell (in CE memory, represented in column-major order).

MCU Interface

In this mode, all scan timings are internal. Signals from the RGB interface are ignored, aside from display RAM writes if enabled. Scan timings are determined by Frame Rate Control 1, Frame Rate Control 2, and Porch Setting.

VSYNC Interface

In this mode, all scan timings are internal except for the frame synchronization pulse. Other signals from the RGB interface are ignored, aside from display RAM writes if enabled.

This mode allows the frame rate alone to be controlled by the RGB interface, while allowing much more flexibility with the timing of the line configuration, pixel clock, and RAM writes.

Note that if the MCU interface timings are not configured to complete a frame faster than the RGB interface, some frame synchronization pulses will be ignored and the framerate will be effectively halved or more.

RAM access

Access to the display RAM is provided to both the RGB and SPI interfaces. Which interface is currently given access is determined by the RM bit of RAM Control, and the data format for each interface is determined by Interface Pixel Format.

Before accessing RAM, a rectangular window should be configured using the Column Address Set and Row Address Set commands. Data is accessed using a Frame Memory Pointer which starts at a corner of the configured window and increments in a major direction configured by the Memory Data Access Control command. Once the opposite edge of the window is reached, it wraps around and increments the pointer in the minor direction. Once the opposite corner of the window has been reached, it wraps around to the beginning.

TI configures a full-screen row-major window by default (starting in the upper-left corner of the screen, moving left to right across a row, and proceeding through each row from top to bottom). This causes the diagonal screen tearing effect commonly seen on the CE, because each line (column) is only partially updated when scanned to the display.

RGB Interface

Each pixel output by the Primecell PL111 is sent over the RGB interface and written to display RAM, if access is enabled. This method has the most performance, and allows using Primecell features such as DMA and color palettes.

The frame synchronization pulse resets the Frame Memory Pointer to the start of the configured window, equivalent to the Write Memory command. Pixels can be written over the RGB interface until the end of the window is reached, after which no more pixels are accepted until the next frame synchronization pulse.

On the CE, an RGB565 data signal is connected to the RGB666 interface by duplicating the MSB of the red and blue components to the LSB of each. If the RGB interface color format is set to 18bpp, this color is written directly to display RAM. On the other hand, if set to 16bpp, the interface interprets the original RGB565 signal and generates the LSBs of red and blue based on the EPF field of RAM Control.

SPI Interface

Pixels can also be sent over the SPI command interface if access is enabled. It has rather slow throughput, but is the only way to write full 18bpp data, or reconfigure the window independently of frame timing. Pixel writes are initiated by the Write Memory or Write Memory Continue commands, and pixels are written as a sequence of parameter bytes.

The SPI interface supports RGB444, RGB565, and RGB666 formats. The first two are expanded to RGB666 based on the EPF field of RAM Control.

Note: Each parameter byte is 9 bits in the SPI protocol, including the leading 1 bit indicating a parameter. X bits are ignored.

RGB444 format (1.5 bytes per pixel): 1RRRRGGGG 1BBBBRRRR 1GGGGBBBB

RGB565 format (2 bytes per pixel): 1RRRRRGGG 1GGGBBBBB (or bytes swapped if the ENDIAN bit of RAM Control is 1)

RGB666 format (3 bytes per pixel): 1RRRRRRXX 1GGGGGGXX 1BBBBBBXX