84PCE:LCD Controller

The CE contains two LCD controllers which work in tandem. This page primarily focuses on the one directly driving the LCD, the Sitronix ST7789.

See also the Primecell PL111 which drives the RGB interface, and the SPI Controller which provides the command interface.

Quick Specs

• Sitronix ST7789 family LCD controller
• TFT color LCD
• Supports RGB and SPI interfaces
• 172,800 bytes internal RAM
• 76,800 pixels (240x320 resolution)
• Power-saving 8-color mode
• 262,144 = 2^18 = 6x6x6 colors
• Data sheet: https://www.rhydolabz.com/documents/33/ST7789.pdf
• Physical LCD: Giant GPM1421C0

Overview

The LCD is a 240x320 pixel display rotated 90 degrees. To make terminology consistent, directions will be described relative to the CE itself, not relative to the display. As such, each scanline appears in a vertical orientation and the display is scanned from left to right. Note that the datasheet will not agree with this page when it comes to the terms "row" and "column". When appropriate, columns (which correspond to scanlines) will be referred to as "lines" to be more consistent with the datasheet.

Operating modes

The controller operates in one of three modes, dictating the refresh rate and scan timing:

RGB Interface

In this mode, the controller accepts the following signals from the Primecell PL111:

• Frame synchronization pulse (CLFP)
• Line synchronization pulse (CLLP)
• Pixel clock (CLCP)
• RGB pixel data (CLD)
• Data enable (CLAC)

This is TI's default setting, and causes the scan timing to be completely controlled by the Primecell.

To prevent scan errors, the Primecell must be configured with at least 240 pixel clocks per line and at least 320 lines per frame, plus the back porch values configured in RGB Interface Control. Note that these pixel clocks and lines are not required to be during active video of the Primecell, as it drives the pixel clock and line sync pulses even during porches.

Active video on the Primecell will drive the data enable and RGB pixel data signals, which are accepted by the RGB interface and written to display RAM, if enabled.

The RGB interface may also be configured with the WO bit of RGB Interface Control to bypass display RAM entirely and output the RGB pixel data signals directly to the display. Of course, this requires precisely a 240x320 active video configuration on the Primecell (in CE memory, represented in column-major order).

MCU Interface

In this mode, all scan timings are internal. Signals from the RGB interface are ignored, aside from display RAM writes if enabled. Scan timings are determined by Frame Rate Control 1, Frame Rate Control 2, and Porch Setting.

VSYNC Interface

In this mode, all scan timings are internal except for the frame synchronization pulse. Other signals from the RGB interface are ignored, aside from display RAM writes if enabled.

This mode allows the frame rate alone to be controlled by the RGB interface, while allowing much more flexibility with the timing of the line configuration, pixel clock, and RAM writes.

Note that if the MCU interface timings are not configured to complete a frame faster than the RGB interface, some frame synchronization pulses will be ignored and the framerate will be effectively halved or more.

RAM access

Access to the display RAM is provided to both the RGB and SPI interfaces. Which interface is currently given access is determined by the RM bit of RAM Control, and the data format for each interface is determined by Interface Pixel Format.

Before accessing RAM, a rectangular window should be configured using the Column Address Set and Row Address Set commands. Data is accessed using a Frame Memory Pointer which starts at a corner of the configured window and moves in the major (X) direction configured by the Memory Data Access Control command. Once the opposite edge of the window is reached, it wraps around and moves the pointer in the minor (Y) direction. Once the opposite corner of the window has been reached, it wraps around to the beginning.

TI configures a full-screen row-major window by default (starting in the upper-left corner of the screen, moving left to right across a row, and proceeding through each row from top to bottom). This causes the diagonal screen tearing effect commonly seen on the CE, because each line (column) is only partially updated when scanned to the display.

RGB Interface

Each pixel output by the Primecell PL111 is sent over the RGB interface and written to display RAM, if access is enabled. This method has the most performance, and allows using Primecell features such as DMA and color palettes.

The frame synchronization pulse resets the Frame Memory Pointer to the start of the configured window, equivalent to the Write Memory command. Pixels can be written over the RGB interface until the end of the window is reached, after which no more pixels are accepted until the next frame synchronization pulse.

On the CE, an RGB565 data signal is connected to the RGB666 interface by duplicating the MSB of the red and blue components to the LSB of each. If the RGB interface color format is set to 18bpp, this color is written directly to display RAM. On the other hand, if set to 16bpp, the interface interprets the original RGB565 signal and generates the LSBs of red and blue based on the EPF field of RAM Control.

SPI Interface

Pixels can also be sent over the SPI command interface if access is enabled. It has rather slow throughput, but is the only way to write full 18bpp data, or reconfigure the window independently of frame timing. Pixel writes are initiated by the Write Memory or Write Memory Continue commands, and pixels are written as a sequence of parameter bytes.

The SPI interface supports RGB444, RGB565, and RGB666 formats. The first two are expanded to RGB666 based on the EPF field of RAM Control.

Note: Each parameter byte is 9 bits in the SPI protocol, including the leading 1 bit indicating a parameter. X bits are ignored.

RGB444 format (1.5 bytes per pixel): 1RRRRGGGG 1BBBBRRRR 1GGGGBBBB

RGB565 format (2 bytes per pixel): 1RRRRRGGG 1GGGBBBBB (or bytes swapped if the ENDIAN bit of RAM Control is 1)

RGB666 format (3 bytes per pixel): 1RRRRRRXX 1GGGGGGXX 1BBBBBBXX

Command List

This is the list of commands usable via the SPI Controller. All command IDs are listed in hexadecimal.

The SPI transfer format is 9 bits per byte. The first 9-bit transfer of every command is a 0 bit followed by the command ID byte, and each following transfer is a 1 bit followed by a parameter byte. All 16-bit parameters are two byte transfers in big-endian order, except for pixel parameters depending on configuration.

It's allowed to send fewer parameter bytes than the maximum the command takes; each parameter byte is immediately applied as it's received. A partial byte transfer can be cancelled safely by disabling the chip select signal (bit 0 of CR2 on the SPI controller).

Read commands don't seem to work properly on CE hardware, so they aren't described here.

00: No Operation

Takes no parameters and does nothing. It can be used to leave the controller in a state where an accidentally sent parameter has no effect.

01: Software Reset

Resets most parameters to their factory default values. Must wait 5ms before sending another command, or 120ms if done in sleep mode.

Display RAM is unaffected by this operation, as well as the Memory Data Access Control and Interface Pixel Format parameters.

10: Sleep In

Enters sleep mode. Must wait 5ms before sending another command.

11: Sleep Out

Exits sleep mode. Must wait 5ms before sending another command. Must wait 120ms before entering sleep mode again.

12: Partial Display Mode On

Enables Partial Display mode on the next frame. See Partial Area and Partial Control.

As a side effect, this resets the Vertical Scroll Start Address to zero.

Optionally uses a different refresh rate in MCU or VSYNC interface modes, according to Frame Rate Control 1 and Porch Setting.

13: Normal Display Mode On

Disables Partial Display mode and Vertical Scroll mode on the next frame.

As a side effect, this resets the Vertical Scroll Start Address to zero.

20: Display Inversion Off

Disables display inversion immediately. This may require frame synchronization to avoid tearing.

21: Display Inversion On

Enables display inversion immediately. This may require frame synchronization to avoid tearing.

26: Gamma Set

Applies a gamma preset.

Parameter byte 1:

Bit	HW Default	TI Default	Description
3:0	01h	02h	GC: Gamma curve. Invalid values default to 01h. 01h: G2.2 02h: G1.8 04h: G2.5 08h: G1.0

28: Display Off

Enables Display Off mode on the next frame. This mode's only effect is forcing all-white frames to be output.

29: Display On

Disables Display Off mode on the next frame.

2A: Column Address Set

Sets the X address range for the memory access window.

The X dimension is always the "major" dimension of the window, depending on the MV bit in Memory Data Access Control. In other words, the Frame Memory Pointer always moves in the X dimension first. The selected dimension also determines whether the maximum value is 239 or 319.

The Address Order configured on the X dimension determines the edge of the display RAM referred to by the 0 address. The X value effectively always increases as it moves through the range, thus the range should always be configured with XS?XE.

Parameter word 1:

Bit	HW Default	TI Default	Description
8:0	0000h	0000h	XS: X Start Address. Should be between 0 and XE, inclusive.

Parameter word 2:

Bit	HW Default	TI Default	Description
8:0	00EFh	013Fh	XE: X End Address. Should be between XS and 239 or 319, inclusive.

2B: Row Address Set

Sets the Y address range for the memory access window.

The Y dimension is always the "minor" dimension of the window, depending on the MV bit in Memory Data Access Control. In other words, the Frame Memory Pointer always moves in the Y dimension second. The selected dimension also determines whether the maximum value is 239 or 319.

The Address Order configured on the Y dimension determines the edge of the display RAM referred to by the 0 address. The Y value effectively always increases as it moves through the range, thus the range should always be configured with YS?YE.

Parameter word 1:

Bit	HW Default	TI Default	Description
8:0	0000h	0000h	YS: Y Start Address. Should be between 0 and YE, inclusive.

Parameter word 2:

Bit	HW Default	TI Default	Description
8:0	013Fh	00EFh	YE: Y End Address. Should be between YS and 239 or 319, inclusive.

2C: Write Memory

Resets the Frame Memory Pointer to (XS, YS) as specified in the Column Address Set and Row Address Set commands.

All parameters to this command are written to memory in order. See RAM Access.

30: Partial Area

Sets the display line range for Partial Mode.

Changes to the partial area only take effect at the next frame start.

Lines inside the inclusive range [PSL, PEL] are displayed normally, and lines outside the range are displayed in a solid white or black depending on the NDL bit in Partial Control.

If PSL>PEL, then the two inclusive ranges [0, PEL] and [PSL, 319] are displayed normally, while the exclusive range (PEL, PSL) is displayed in solid white or black.

If the ML bit is set in Memory Data Access Control, line 0 refers to the right edge of the display, and line numbers increase to the left.

Parameter word 1:

Bit	HW Default	TI Default	Description
8:0	0000h	N/A	PSL: Partial Start Line. Should be between 0 and 319, inclusive.

Parameter word 2:

Bit	HW Default	TI Default	Description
8:0	013Fh	N/A	PEL: Partial End Line. Should be between 0 and 319, inclusive.

33: Vertical Scrolling Definition

Sets the display line range for Vertical Scroll mode. Note since the display is rotated, this is actually a horizontal scroll mode.

Changes to the scroll area only take effect at the next frame start.

The TFA lines on the left side of the screen are displayed normally, as well as the TBA lines on the right side of the screen. The lines in the middle range [TFA, 320-BFA) participate in horizontal scrolling.

If the ML bit is set in Memory Data Access Control, the scrolling range is interpreted from right to left, making it [TFA, 320-BFA) under normal line numbering.

The datasheet specifies that VSA should hold the number of lines in the scrolling range such that TFA+VSA+BFA=320, but VSA seems to have no effect in practice.

Parameter word 1:

Bit	HW Default	TI Default	Description
8:0	0000h	N/A	TFA: Top Fixed Area. Should be between 0 and 320-BFA, inclusive.

Parameter word 2:

Bit	HW Default	TI Default	Description
8:0	013Fh	N/A	VSA: Vertical Scrolling Area. Seems to be ignored, but recommended to set to 320-(TFA+BFA).

Parameter word 3:

Bit	HW Default	TI Default	Description
8:0	013Fh	N/A	BFA: Bottom Fixed Area. Should be between 0 and 320-TFA, inclusive.

34: Tearing Effect Line Off

Disables the Tearing Effect output signal. Unlikely this signal can be used on CE.

35: Tearing Effect Line On

Enables the Tearing Effect output signal. Unlikely this signal can be used on CE.

36: Memory Data Access Control

Determines the behavior of the Frame Memory Pointer, display scan order, and RGB/BGR output.

Note: Most bits in this register can be inverted by bits in LCM Control.

Parameter byte 1:

Bit	HW Default	TI Default	Description
2	0	0	MH: Display data latch order. 0 means scan each line from top to bottom, 1 means from bottom to top. This does not change the order of the display pixels unless in RGB Interface RAM bypass mode. Can be inverted by the XMH bit in LCM Control.
3	0	1	RGB: RGB/BGR order. 0 means RGB order, 1 means BGR order. Can be inverted by the XBGR bit in LCM Control. Important: TI-OS inverts this bit by default!
4	0	0	ML: Line address order. 0 means scan the frame from left to right, 1 means from right to left. This does not change the order of the displayed pixels unless in RGB Interface RAM bypass mode. Some features are affected by line address order, see Partial Area and Vertical Scrolling Definition.
5	0	0	MV: Page/column order. 0 means X address moves vertically and Y address moves horizontally, 1 means X address moves horizontally and Y address moves vertically. Can be inverted by the XMV bit in LCM Control. Important: TI-OS inverts this bit by default! Changing this before a Write Memory Continue effectively swaps the horizontal and vertical coordinates of the Frame Memory Pointer.
6	0	0	MX: Column address order. 0 means addresses increase from top to bottom, 1 means addresses increase from bottom to top. Can be inverted by the XMX bit in LCM Control. Changing this before a Write Memory Continue leaves the Frame Memory Pointer at the same physical address, meaning the X or Y address is subtracted from 239 in the new coordinate system.
7	0	0	MY: Page address order. 0 means addresses increase from left to right, 1 means addresses increase from right to left. Can be inverted by the XMY bit in LCM Control. Changing this before a Write Memory Continue leaves the Frame Memory Pointer at the same physical address, meaning the X or Y address is subtracted from 319 in the new coordinate system.

37: Vertical Scroll Start Address

Sets the starting line address in frame memory to be displayed in the scroll area in Vertical Scroll mode. Note since the display is rotated, this is actually a horizontal scroll mode.

Changes to the scroll address only take effect at the next frame start.

See Vertical Scrolling Definition to set up the scroll area.

VSP is set to the line to display on the left-hand side of the scroll area between [TFA, 320-BFA). This means setting VSP=TFA means no scrolling, and increasing the value scrolls the area to the left.

If the ML bit is set in Memory Data Access Control, the line address is interpreted from right to left and VSP is the line to display on the right-hand side, so while VSP=TFA still means no scrolling, increasing the value scrolls the area to the right instead.

The scrolling is designed such that only the lines within the scroll area are rotated; when line 320-BFA is reached in frame memory, the line address returns to TFA. Strictly speaking, the first time in a frame that the line address is at least 320-BFA, (320-BFA)-TFA is subtracted from the line address. This can be useful knowledge when using the scroll mode for unintended behavior like showing the same lines in multiple parts of the screen.

Parameter word 1:

Bit	HW Default	TI Default	Description
8:0	0000h	N/A	VSP: Vertical Scroll Pointer. Should be between [TFA, 320-BFA), but can be set outside that range for other effects.

38: Idle Mode Off

Disables Idle Mode, allowing full range of color display.

39: Idle Mode On

Enables Idle Mode, displaying 8 colors based on the most significant bit of each color component.

Optionally uses a different refresh rate in MCU or VSYNC interface modes, according to Frame Rate Control 1 and Porch Setting.