Difference between revisions of "83Plus:Ports:27"
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(I don't know who thought only values up to 12h were valid, but my actual crowd-sourced experiments say otherwise.) |
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=== Write Values === | === Write Values === | ||
| − | * [00h - | + | * [00h - FFh]: The value times 64 equals the number of bytes that get re-mapped starting from FFFFh. So a value of 12h would re-map data in FB80h - FFFFh. |
== Comments == | == Comments == | ||
This bares more than resemblance to port 28h so I guess they were meant to be used together. | This bares more than resemblance to port 28h so I guess they were meant to be used together. | ||
| + | |||
| + | 64*256 = 16320, which is 64 bytes less than 65536. So you can't use this to completely override port 5. I don't why you would, but it tripped me up once while writing the experiments. | ||
Port 27 and 28 appear to have no effect in memory mapping mode 1. | Port 27 and 28 appear to have no effect in memory mapping mode 1. | ||
Revision as of 21:53, 13 March 2013
| This port only exists as a distinct port on the TI-83 Plus Silver Edition, the TI-84 Plus, and the TI-84 Plus Silver Edition. On the standard TI-83 Plus, it acts as a shadow of port 07. |
Contents
Synopsis
Port Number: 27h
Function: Block Memory Mapping C000h
By an order of 64 bytes per block, this port can re-map data from ram page 0 to reflect the memory C000h - FFFFh addresses without regard to the contents of port 5. This port does not map the entire page, but only 64 bytes times the value in this port. It maps it starting from high memory (FFFFh) to low.
Read Values
- This port reads the last value written to it.
Write Values
- [00h - FFh]: The value times 64 equals the number of bytes that get re-mapped starting from FFFFh. So a value of 12h would re-map data in FB80h - FFFFh.
Comments
This bares more than resemblance to port 28h so I guess they were meant to be used together.
64*256 = 16320, which is 64 bytes less than 65536. So you can't use this to completely override port 5. I don't why you would, but it tripped me up once while writing the experiments.
Port 27 and 28 appear to have no effect in memory mapping mode 1.
Credits and Contributions
- James Montelongo
