Difference between revisions of "84PCE:Ports:0006"
From WikiTI
(→Details) |
(Change based on known behavior, the other bits should be investigated more.) |
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=== Bit [2] === | === Bit [2] === | ||
| − | Set this bit to enable display updates if bit 1 is ever reset. | + | Set this bit to enable display updates if bit 1 is ever reset. ??? |
| + | |||
| + | This bit is known to unlock protected mmio ports, such as [[84PCE:Ports:2000|SHA256]]. | ||
| + | It is cleared every time the boot code interrupt handler runs. | ||
=== Bit [3] === | === Bit [3] === | ||
| Line 22: | Line 25: | ||
=== Bit [4] === | === Bit [4] === | ||
| − | Flash lock status. | + | <s>Flash lock status.</s> |
=== Bits [7:3] === | === Bits [7:3] === | ||
Writes do not latch; no apparent effect. | Writes do not latch; no apparent effect. | ||
Revision as of 00:13, 8 August 2017
Contents
Synopsis
Port Number: 0006
Function: Unknown
Details
This port seems to affect the display refresh.
Bit [0]
Latches value written, no apparent effect.
Bit [1]
Reset this bit to disable display upadates.
Bit [2]
Set this bit to enable display updates if bit 1 is ever reset. ???
This bit is known to unlock protected mmio ports, such as SHA256. It is cleared every time the boot code interrupt handler runs.
Bit [3]
Writes do not latch; no apparent effect.
Bit [4]
Flash lock status.
Bits [7:3]
Writes do not latch; no apparent effect.
